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[/] [ethmac/] [tags/] [rel_10/] [rtl/] - Rev 338

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Rev	Log message	Author	Age	Path
338		root	5469d 16h	/ethmac/tags/rel_10/rtl/
335	New directory structure.	root	5526d 21h	/ethmac/tags/rel_10/rtl/
247	This commit was manufactured by cvs2svn to create tag 'rel_10'.		7832d 17h	/ethmac/tags/rel_10/rtl/
246	Since r_Rst bit is not used any more, default value is changed to 0xa000.	mohor	7832d 17h	/ethmac/tags/rel_10/rtl/
244	r_Rst signal does not reset any module any more and is removed from the design.	mohor	7833d 13h	/ethmac/tags/rel_10/rtl/
242	Late collision is reported only when not in the full duplex. Sample is taken (for status) as soon as MRxDV is not valid (regardless of the received byte cnt).	tadejm	7834d 09h	/ethmac/tags/rel_10/rtl/
241	StartIdle state changed (not important the size of the packet). StartData1 activates only while ByteCnt is smaller than the MaxFrame.	tadejm	7834d 09h	/ethmac/tags/rel_10/rtl/
240	All modules are reset with wb_rst instead of the r_Rst. Exception is MII module.	tadejm	7834d 09h	/ethmac/tags/rel_10/rtl/
239	RxError is not generated when small frame reception is enabled and small frames are received.	tadejm	7834d 09h	/ethmac/tags/rel_10/rtl/
238	Defines fixed to use generic RAM by default.	mohor	7846d 13h	/ethmac/tags/rel_10/rtl/
236	State machine goes from idle to the defer state when CarrierSense is 1. FCS (CRC appending) fixed to check the CrcEn bit also when padding is necessery.	mohor	7848d 18h	/ethmac/tags/rel_10/rtl/
232	fpga define added.	mohor	7854d 12h	/ethmac/tags/rel_10/rtl/
229	case changed to casex.	mohor	7860d 10h	/ethmac/tags/rel_10/rtl/
227	Changed BIST scan signals.	tadejm	7860d 14h	/ethmac/tags/rel_10/rtl/
226	Igor added WB burst support and repaired BUG when handling TX under-run and retry.	tadejm	7860d 15h	/ethmac/tags/rel_10/rtl/
221	TxStatus is written after last access to the TX fifo is finished (in case of abort or retry). TxDone is fixed.	mohor	7864d 15h	/ethmac/tags/rel_10/rtl/
219	txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file, TxDone and TxRetry are generated after the current WISHBONE access is finished.	mohor	7867d 16h	/ethmac/tags/rel_10/rtl/
218	Typo error fixed. (When using Bist)	mohor	7867d 18h	/ethmac/tags/rel_10/rtl/
214	Signals for WISHBONE B3 compliant interface added.	mohor	7868d 14h	/ethmac/tags/rel_10/rtl/
213	Defines changed to have ETH_ prolog. ETH_WISHBONE_B# define added.	mohor	7868d 14h	/ethmac/tags/rel_10/rtl/

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[/] [ethmac/] [tags/] [rel_10/] [rtl/] - Rev 338

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