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[/] [ethmac/] [tags/] [rel_10/] [rtl/] - Rev 338

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338 root 4046d 09h /ethmac/tags/rel_10/rtl/
335 New directory structure. root 4103d 14h /ethmac/tags/rel_10/rtl/
247 This commit was manufactured by cvs2svn to create tag 'rel_10'. 6409d 10h /ethmac/tags/rel_10/rtl/
246 Since r_Rst bit is not used any more, default value is changed to 0xa000. mohor 6409d 10h /ethmac/tags/rel_10/rtl/
244 r_Rst signal does not reset any module any more and is removed from the design. mohor 6410d 06h /ethmac/tags/rel_10/rtl/
242 Late collision is reported only when not in the full duplex.
Sample is taken (for status) as soon as MRxDV is not valid (regardless
of the received byte cnt).
tadejm 6411d 02h /ethmac/tags/rel_10/rtl/
241 StartIdle state changed (not important the size of the packet).
StartData1 activates only while ByteCnt is smaller than the MaxFrame.
tadejm 6411d 02h /ethmac/tags/rel_10/rtl/
240 All modules are reset with wb_rst instead of the r_Rst. Exception is MII module. tadejm 6411d 02h /ethmac/tags/rel_10/rtl/
239 RxError is not generated when small frame reception is enabled and small
frames are received.
tadejm 6411d 02h /ethmac/tags/rel_10/rtl/
238 Defines fixed to use generic RAM by default. mohor 6423d 06h /ethmac/tags/rel_10/rtl/
236 State machine goes from idle to the defer state when CarrierSense is 1. FCS (CRC appending) fixed to check the CrcEn bit also when padding is necessery. mohor 6425d 11h /ethmac/tags/rel_10/rtl/
232 fpga define added. mohor 6431d 05h /ethmac/tags/rel_10/rtl/
229 case changed to casex. mohor 6437d 03h /ethmac/tags/rel_10/rtl/
227 Changed BIST scan signals. tadejm 6437d 07h /ethmac/tags/rel_10/rtl/
226 Igor added WB burst support and repaired BUG when handling TX under-run and retry. tadejm 6437d 08h /ethmac/tags/rel_10/rtl/
221 TxStatus is written after last access to the TX fifo is finished (in case of abort
or retry). TxDone is fixed.
mohor 6441d 08h /ethmac/tags/rel_10/rtl/
219 txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,
TxDone and TxRetry are generated after the current WISHBONE access is
finished.
mohor 6444d 09h /ethmac/tags/rel_10/rtl/
218 Typo error fixed. (When using Bist) mohor 6444d 11h /ethmac/tags/rel_10/rtl/
214 Signals for WISHBONE B3 compliant interface added. mohor 6445d 07h /ethmac/tags/rel_10/rtl/
213 Defines changed to have ETH_ prolog.
ETH_WISHBONE_B# define added.
mohor 6445d 07h /ethmac/tags/rel_10/rtl/
212 Minor $display change. mohor 6445d 07h /ethmac/tags/rel_10/rtl/
211 Bist added. mohor 6445d 08h /ethmac/tags/rel_10/rtl/
210 BIST added. mohor 6445d 08h /ethmac/tags/rel_10/rtl/
204 ETH_VIRTUAL_SILICON_RAM supported (for ASIC implementation). mohor 6462d 06h /ethmac/tags/rel_10/rtl/
203 Virtual Silicon RAM might be used in the ASIC implementation of the ethernet
core.
mohor 6462d 06h /ethmac/tags/rel_10/rtl/
202 CsMiss added. When address between 0x800 and 0xfff is accessed within
Ethernet Core, error acknowledge is generated.
mohor 6465d 07h /ethmac/tags/rel_10/rtl/
168 CarrierSenseLost bug fixed when operating in full duplex mode. mohor 6473d 09h /ethmac/tags/rel_10/rtl/
167 Sometimes both RxB_IRQ and RxE_IRQ were activated. Bug fixed. mohor 6474d 10h /ethmac/tags/rel_10/rtl/
166 Reception is possible after RxPointer is read and not after BD is read. For
that reason RxBDReady is changed to RxReady.
Busy_IRQ interrupt connected. When there is no RxBD ready and frame
comes, interrupt is generated.
mohor 6475d 10h /ethmac/tags/rel_10/rtl/
165 HASH improvement needed. mohor 6475d 13h /ethmac/tags/rel_10/rtl/

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