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[/] [ethmac/] [tags/] [rel_10] - Rev 221

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Rev Log message Author Age Path
221 TxStatus is written after last access to the TX fifo is finished (in case of abort
or retry). TxDone is fixed.		 mohor 7874d 07h /ethmac/tags/rel_10
219 txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,
TxDone and TxRetry are generated after the current WISHBONE access is
finished.		 mohor 7877d 08h /ethmac/tags/rel_10
218 Typo error fixed. (When using Bist) mohor 7877d 10h /ethmac/tags/rel_10
217 Bist supported. mohor 7877d 10h /ethmac/tags/rel_10
216 Bist signals added. mohor 7877d 10h /ethmac/tags/rel_10
215 Bist supported. mohor 7877d 11h /ethmac/tags/rel_10
214 Signals for WISHBONE B3 compliant interface added. mohor 7878d 07h /ethmac/tags/rel_10
213 Defines changed to have ETH_ prolog.
ETH_WISHBONE_B# define added.		 mohor 7878d 07h /ethmac/tags/rel_10
212 Minor $display change. mohor 7878d 07h /ethmac/tags/rel_10
211 Bist added. mohor 7878d 07h /ethmac/tags/rel_10
210 BIST added. mohor 7878d 07h /ethmac/tags/rel_10
209 Just back-up; not completed testbench and some testcases are not
wotking properly yet.		 tadejm 7879d 10h /ethmac/tags/rel_10
208 Virtual Silicon RAMs moved to lib directory tadej 7895d 04h /ethmac/tags/rel_10
207 Virtual Silicon RAM support fixed tadej 7895d 04h /ethmac/tags/rel_10
206 Virtual Silicon RAM added to the simulation. mohor 7895d 04h /ethmac/tags/rel_10
205 ETH_VIRTUAL_SILICON_RAM supported. mohor 7895d 05h /ethmac/tags/rel_10
204 ETH_VIRTUAL_SILICON_RAM supported (for ASIC implementation). mohor 7895d 05h /ethmac/tags/rel_10
203 Virtual Silicon RAM might be used in the ASIC implementation of the ethernet
core.		 mohor 7895d 05h /ethmac/tags/rel_10
202 CsMiss added. When address between 0x800 and 0xfff is accessed within
Ethernet Core, error acknowledge is generated.		 mohor 7898d 06h /ethmac/tags/rel_10
201 Core size added to the document. mohor 7898d 07h /ethmac/tags/rel_10

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