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[/] [ethmac/] [tags/] [rel_10] - Rev 224

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224 Signals for a wave window in Modelsim. tadejm 7867d 23h /ethmac/tags/rel_10
223 Some code changed due to bug fixes. tadejm 7867d 23h /ethmac/tags/rel_10
221 TxStatus is written after last access to the TX fifo is finished (in case of abort
or retry). TxDone is fixed.		 mohor 7871d 21h /ethmac/tags/rel_10
219 txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,
TxDone and TxRetry are generated after the current WISHBONE access is
finished.		 mohor 7874d 21h /ethmac/tags/rel_10
218 Typo error fixed. (When using Bist) mohor 7874d 23h /ethmac/tags/rel_10
217 Bist supported. mohor 7874d 23h /ethmac/tags/rel_10
216 Bist signals added. mohor 7874d 23h /ethmac/tags/rel_10
215 Bist supported. mohor 7875d 00h /ethmac/tags/rel_10
214 Signals for WISHBONE B3 compliant interface added. mohor 7875d 20h /ethmac/tags/rel_10
213 Defines changed to have ETH_ prolog.
ETH_WISHBONE_B# define added.		 mohor 7875d 20h /ethmac/tags/rel_10
212 Minor $display change. mohor 7875d 20h /ethmac/tags/rel_10
211 Bist added. mohor 7875d 20h /ethmac/tags/rel_10
210 BIST added. mohor 7875d 20h /ethmac/tags/rel_10
209 Just back-up; not completed testbench and some testcases are not
wotking properly yet.		 tadejm 7877d 00h /ethmac/tags/rel_10
208 Virtual Silicon RAMs moved to lib directory tadej 7892d 17h /ethmac/tags/rel_10
207 Virtual Silicon RAM support fixed tadej 7892d 18h /ethmac/tags/rel_10
206 Virtual Silicon RAM added to the simulation. mohor 7892d 18h /ethmac/tags/rel_10
205 ETH_VIRTUAL_SILICON_RAM supported. mohor 7892d 18h /ethmac/tags/rel_10
204 ETH_VIRTUAL_SILICON_RAM supported (for ASIC implementation). mohor 7892d 18h /ethmac/tags/rel_10
203 Virtual Silicon RAM might be used in the ASIC implementation of the ethernet
core.		 mohor 7892d 18h /ethmac/tags/rel_10

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