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[/] [ethmac/] [tags/] [rel_10] - Rev 243

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Rev Log message Author Age Path
243 Late collision is not reported any more. tadejm 7857d 05h /ethmac/tags/rel_10
242 Late collision is reported only when not in the full duplex.
Sample is taken (for status) as soon as MRxDV is not valid (regardless
of the received byte cnt).		 tadejm 7857d 20h /ethmac/tags/rel_10
241 StartIdle state changed (not important the size of the packet).
StartData1 activates only while ByteCnt is smaller than the MaxFrame.		 tadejm 7857d 20h /ethmac/tags/rel_10
240 All modules are reset with wb_rst instead of the r_Rst. Exception is MII module. tadejm 7857d 20h /ethmac/tags/rel_10
239 RxError is not generated when small frame reception is enabled and small
frames are received.		 tadejm 7857d 20h /ethmac/tags/rel_10
238 Defines fixed to use generic RAM by default. mohor 7870d 00h /ethmac/tags/rel_10
236 State machine goes from idle to the defer state when CarrierSense is 1. FCS (CRC appending) fixed to check the CrcEn bit also when padding is necessery. mohor 7872d 05h /ethmac/tags/rel_10
235 rev 4. mohor 7872d 20h /ethmac/tags/rel_10
234 Figure list assed to the revision 3. mohor 7873d 04h /ethmac/tags/rel_10
233 Revision 0.3 released. Some figures added. mohor 7873d 04h /ethmac/tags/rel_10
232 fpga define added. mohor 7877d 23h /ethmac/tags/rel_10
231 Description of Core Modules added (figure). mohor 7880d 01h /ethmac/tags/rel_10
229 case changed to casex. mohor 7883d 21h /ethmac/tags/rel_10
227 Changed BIST scan signals. tadejm 7884d 01h /ethmac/tags/rel_10
226 Igor added WB burst support and repaired BUG when handling TX under-run and retry. tadejm 7884d 02h /ethmac/tags/rel_10
225 Some minor changes. tadejm 7884d 03h /ethmac/tags/rel_10
224 Signals for a wave window in Modelsim. tadejm 7884d 04h /ethmac/tags/rel_10
223 Some code changed due to bug fixes. tadejm 7884d 04h /ethmac/tags/rel_10
221 TxStatus is written after last access to the TX fifo is finished (in case of abort
or retry). TxDone is fixed.		 mohor 7888d 02h /ethmac/tags/rel_10
219 txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,
TxDone and TxRetry are generated after the current WISHBONE access is
finished.		 mohor 7891d 03h /ethmac/tags/rel_10
218 Typo error fixed. (When using Bist) mohor 7891d 05h /ethmac/tags/rel_10
217 Bist supported. mohor 7891d 05h /ethmac/tags/rel_10
216 Bist signals added. mohor 7891d 05h /ethmac/tags/rel_10
215 Bist supported. mohor 7891d 05h /ethmac/tags/rel_10
214 Signals for WISHBONE B3 compliant interface added. mohor 7892d 01h /ethmac/tags/rel_10
213 Defines changed to have ETH_ prolog.
ETH_WISHBONE_B# define added.		 mohor 7892d 01h /ethmac/tags/rel_10
212 Minor $display change. mohor 7892d 01h /ethmac/tags/rel_10
211 Bist added. mohor 7892d 02h /ethmac/tags/rel_10
210 BIST added. mohor 7892d 02h /ethmac/tags/rel_10
209 Just back-up; not completed testbench and some testcases are not
wotking properly yet.		 tadejm 7893d 05h /ethmac/tags/rel_10

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