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[/] [ethmac/] [tags/] [rel_11/] - Rev 241

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241 StartIdle state changed (not important the size of the packet).
StartData1 activates only while ByteCnt is smaller than the MaxFrame.		 tadejm 7838d 21h /ethmac/tags/rel_11
240 All modules are reset with wb_rst instead of the r_Rst. Exception is MII module. tadejm 7838d 21h /ethmac/tags/rel_11
239 RxError is not generated when small frame reception is enabled and small
frames are received.		 tadejm 7838d 21h /ethmac/tags/rel_11
238 Defines fixed to use generic RAM by default. mohor 7851d 01h /ethmac/tags/rel_11
236 State machine goes from idle to the defer state when CarrierSense is 1. FCS (CRC appending) fixed to check the CrcEn bit also when padding is necessery. mohor 7853d 07h /ethmac/tags/rel_11
235 rev 4. mohor 7853d 21h /ethmac/tags/rel_11
234 Figure list assed to the revision 3. mohor 7854d 05h /ethmac/tags/rel_11
233 Revision 0.3 released. Some figures added. mohor 7854d 06h /ethmac/tags/rel_11
232 fpga define added. mohor 7859d 01h /ethmac/tags/rel_11
231 Description of Core Modules added (figure). mohor 7861d 02h /ethmac/tags/rel_11
229 case changed to casex. mohor 7864d 23h /ethmac/tags/rel_11
227 Changed BIST scan signals. tadejm 7865d 02h /ethmac/tags/rel_11
226 Igor added WB burst support and repaired BUG when handling TX under-run and retry. tadejm 7865d 04h /ethmac/tags/rel_11
225 Some minor changes. tadejm 7865d 04h /ethmac/tags/rel_11
224 Signals for a wave window in Modelsim. tadejm 7865d 05h /ethmac/tags/rel_11
223 Some code changed due to bug fixes. tadejm 7865d 06h /ethmac/tags/rel_11
221 TxStatus is written after last access to the TX fifo is finished (in case of abort
or retry). TxDone is fixed.		 mohor 7869d 03h /ethmac/tags/rel_11
219 txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,
TxDone and TxRetry are generated after the current WISHBONE access is
finished.		 mohor 7872d 04h /ethmac/tags/rel_11
218 Typo error fixed. (When using Bist) mohor 7872d 06h /ethmac/tags/rel_11
217 Bist supported. mohor 7872d 06h /ethmac/tags/rel_11
216 Bist signals added. mohor 7872d 06h /ethmac/tags/rel_11
215 Bist supported. mohor 7872d 07h /ethmac/tags/rel_11
214 Signals for WISHBONE B3 compliant interface added. mohor 7873d 03h /ethmac/tags/rel_11
213 Defines changed to have ETH_ prolog.
ETH_WISHBONE_B# define added.		 mohor 7873d 03h /ethmac/tags/rel_11
212 Minor $display change. mohor 7873d 03h /ethmac/tags/rel_11
211 Bist added. mohor 7873d 03h /ethmac/tags/rel_11
210 BIST added. mohor 7873d 03h /ethmac/tags/rel_11
209 Just back-up; not completed testbench and some testcases are not
wotking properly yet.		 tadejm 7874d 06h /ethmac/tags/rel_11
208 Virtual Silicon RAMs moved to lib directory tadej 7890d 00h /ethmac/tags/rel_11
207 Virtual Silicon RAM support fixed tadej 7890d 00h /ethmac/tags/rel_11

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