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[/] [ethmac/] [tags/] [rel_11/] - Rev 33

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Rev	Log message	Author	Age	Path
33	ETH_RX_BD_ADR register deleted. ETH_RX_BD_NUM is used instead.	mohor	8191d 05h	/ethmac/tags/rel_11/
32	ETH_RX_BD_ADR register deleted. ETH_RX_BD_NUM is used instead.	mohor	8191d 05h	/ethmac/tags/rel_11/
31	RX_BD_NUM register added instead of the RB_BD_ADDR.	mohor	8191d 06h	/ethmac/tags/rel_11/
30	BD section updated.	mohor	8193d 02h	/ethmac/tags/rel_11/
29	Generic memory model is used. Defines are changed for the same reason.	mohor	8213d 01h	/ethmac/tags/rel_11/
28	New release. Name changed to lower case.	mohor	8215d 17h	/ethmac/tags/rel_11/
27	File names changed to lower case.	mohor	8215d 17h	/ethmac/tags/rel_11/
26	First release of product brief.	mohor	8215d 17h	/ethmac/tags/rel_11/
25	First release of product brief.	mohor	8215d 17h	/ethmac/tags/rel_11/
24	Log file added.	mohor	8238d 04h	/ethmac/tags/rel_11/
23	Number of addresses (wb_adr_i) minimized.	mohor	8238d 04h	/ethmac/tags/rel_11/
22	eth_timescale.v changed to timescale.v This is done because of the simulation of the few cores in a one joined project.	mohor	8238d 07h	/ethmac/tags/rel_11/
21	Status signals changed, Adress decoding changed, interrupt controller added.	mohor	8239d 04h	/ethmac/tags/rel_11/
20	Defines changed (All precede with ETH_). Small changes because some tools generate warnings when two operands are together. Synchronization between two clocks domains in eth_wishbonedma.v is changed (due to ASIC demands).	mohor	8263d 01h	/ethmac/tags/rel_11/
19	Defines changed (All precede with ETH_). Small changes because some tools generate warnings when two operands are together. Synchronization between two clocks domains in eth_wishbonedma.v is changed (due to ASIC demands).	mohor	8263d 01h	/ethmac/tags/rel_11/
18	Few little NCSIM warnings fixed.	mohor	8276d 01h	/ethmac/tags/rel_11/
17	Signal names changed on the top level for easier pad insertion (ASIC).	mohor	8303d 02h	/ethmac/tags/rel_11/
16	"else" was missing within the always block in file eth_wishbonedma.v.	mohor	8310d 07h	/ethmac/tags/rel_11/
15	A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex). Include files fixed to contain no path. File names and module names changed ta have a eth_ prologue in the name. File eth_timescale.v is used to define timescale All pin names on the top module are changed to contain _I, _O or _OE at the end. Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O and Mdo_OE. The bidirectional signal must be created on the top level. This is done due to the ASIC tools.	mohor	8312d 01h	/ethmac/tags/rel_11/
14	Unconnected signals are now connected.	mohor	8316d 06h	/ethmac/tags/rel_11/
13	New directory structure. Files upodated and put together.	mohor	8318d 15h	/ethmac/tags/rel_11/
12	Directory structure changed. Files checked and joind together.	mohor	8318d 18h	/ethmac/tags/rel_11/
11	Directory structure changed. Files checked and joind together.	mohor	8318d 18h	/ethmac/tags/rel_11/
10	Directory structure changed. Files checked and joind together.	mohor	8318d 18h	/ethmac/tags/rel_11/
9	Documentation updated to be synchronized to the verilog files.	mohor	8346d 03h	/ethmac/tags/rel_11/
8	Version 1.3. Status registers added. DMA channels 2 and 3 are not used any more. Things that are implementation specific were deleted out of the document.	mohor	8373d 07h	/ethmac/tags/rel_11/
7	Version 1.3. Status registers added. DMA channels 2 and 3 are not used any more. Things that are implementation specific were deleted out of the document.	mohor	8373d 08h	/ethmac/tags/rel_11/
6	no message	mohor	8373d 08h	/ethmac/tags/rel_11/
5	This is a Microsoft version of the spec in the pdf format.	mohor	8377d 17h	/ethmac/tags/rel_11/
4	deleted	mohor	8377d 17h	/ethmac/tags/rel_11/

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[/] [ethmac/] [tags/] [rel_11/] - Rev 33

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