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Rev Log message Author Age Path
17 Signal names changed on the top level for easier pad insertion (ASIC). mohor 8313d 00h /ethmac/tags/rel_11/
16 "else" was missing within the always block in file eth_wishbonedma.v. mohor 8320d 06h /ethmac/tags/rel_11/
15 A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
Include files fixed to contain no path.
File names and module names changed ta have a eth_ prologue in the name.
File eth_timescale.v is used to define timescale
All pin names on the top module are changed to contain _I, _O or _OE at the end.
Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
and Mdo_OE. The bidirectional signal must be created on the top level. This
is done due to the ASIC tools.		 mohor 8321d 23h /ethmac/tags/rel_11/
14 Unconnected signals are now connected. mohor 8326d 05h /ethmac/tags/rel_11/
13 New directory structure. Files upodated and put together. mohor 8328d 13h /ethmac/tags/rel_11/
12 Directory structure changed. Files checked and joind together. mohor 8328d 16h /ethmac/tags/rel_11/
11 Directory structure changed. Files checked and joind together. mohor 8328d 16h /ethmac/tags/rel_11/
10 Directory structure changed. Files checked and joind together. mohor 8328d 17h /ethmac/tags/rel_11/
9 Documentation updated to be synchronized to the verilog files. mohor 8356d 01h /ethmac/tags/rel_11/
8 Version 1.3. Status registers added. DMA channels 2 and 3 are not used
any more. Things that are implementation specific were deleted out of the
document.		 mohor 8383d 06h /ethmac/tags/rel_11/

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