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38 Initial version. Equals to eth_wishbonedma.v at this moment. mohor 8151d 07h /ethmac/tags/rel_11/
37 Link in the header changed. mohor 8151d 07h /ethmac/tags/rel_11/
36 TX_BD_NUM register added instead of the RB_BD_ADDR. mohor 8197d 05h /ethmac/tags/rel_11/
35 RX_BD_NUM changed to TX_BD_NUM. Few typos corrected. mohor 8200d 03h /ethmac/tags/rel_11/
34 RX_BD_NUM changed to TX_BD_NUM (holds number of TX descriptors
instead of the number of RX descriptors).		 mohor 8200d 03h /ethmac/tags/rel_11/
33 ETH_RX_BD_ADR register deleted. ETH_RX_BD_NUM is used instead. mohor 8200d 07h /ethmac/tags/rel_11/
32 ETH_RX_BD_ADR register deleted. ETH_RX_BD_NUM is used instead. mohor 8200d 08h /ethmac/tags/rel_11/
31 RX_BD_NUM register added instead of the RB_BD_ADDR. mohor 8200d 08h /ethmac/tags/rel_11/
30 BD section updated. mohor 8202d 05h /ethmac/tags/rel_11/
29 Generic memory model is used. Defines are changed for the same reason. mohor 8222d 04h /ethmac/tags/rel_11/
28 New release. Name changed to lower case. mohor 8224d 19h /ethmac/tags/rel_11/
27 File names changed to lower case. mohor 8224d 19h /ethmac/tags/rel_11/
26 First release of product brief. mohor 8224d 19h /ethmac/tags/rel_11/
25 First release of product brief. mohor 8224d 19h /ethmac/tags/rel_11/
24 Log file added. mohor 8247d 06h /ethmac/tags/rel_11/
23 Number of addresses (wb_adr_i) minimized. mohor 8247d 07h /ethmac/tags/rel_11/
22 eth_timescale.v changed to timescale.v This is done because of the
simulation of the few cores in a one joined project.		 mohor 8247d 09h /ethmac/tags/rel_11/
21 Status signals changed, Adress decoding changed, interrupt controller
added.		 mohor 8248d 06h /ethmac/tags/rel_11/
20 Defines changed (All precede with ETH_). Small changes because some
tools generate warnings when two operands are together. Synchronization
between two clocks domains in eth_wishbonedma.v is changed (due to ASIC
demands).		 mohor 8272d 03h /ethmac/tags/rel_11/
19 Defines changed (All precede with ETH_). Small changes because some
tools generate warnings when two operands are together. Synchronization
between two clocks domains in eth_wishbonedma.v is changed (due to ASIC
demands).		 mohor 8272d 03h /ethmac/tags/rel_11/
18 Few little NCSIM warnings fixed. mohor 8285d 04h /ethmac/tags/rel_11/
17 Signal names changed on the top level for easier pad insertion (ASIC). mohor 8312d 04h /ethmac/tags/rel_11/
16 "else" was missing within the always block in file eth_wishbonedma.v. mohor 8319d 09h /ethmac/tags/rel_11/
15 A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
Include files fixed to contain no path.
File names and module names changed ta have a eth_ prologue in the name.
File eth_timescale.v is used to define timescale
All pin names on the top module are changed to contain _I, _O or _OE at the end.
Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
and Mdo_OE. The bidirectional signal must be created on the top level. This
is done due to the ASIC tools.		 mohor 8321d 03h /ethmac/tags/rel_11/
14 Unconnected signals are now connected. mohor 8325d 08h /ethmac/tags/rel_11/
13 New directory structure. Files upodated and put together. mohor 8327d 17h /ethmac/tags/rel_11/
12 Directory structure changed. Files checked and joind together. mohor 8327d 20h /ethmac/tags/rel_11/
11 Directory structure changed. Files checked and joind together. mohor 8327d 20h /ethmac/tags/rel_11/
10 Directory structure changed. Files checked and joind together. mohor 8327d 21h /ethmac/tags/rel_11/
9 Documentation updated to be synchronized to the verilog files. mohor 8355d 05h /ethmac/tags/rel_11/

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