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[/] [ethmac/] [tags/] [rel_11/] [bench/] - Rev 180

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51 Added separate tests for Multicast, Unicast, Broadcast billditt 6457d 18h /ethmac/tags/rel_11/bench/
49 HASH0 and HASH1 register read/write added. mohor 6459d 18h /ethmac/tags/rel_11/bench/
41 non-DMA host interface added. Select the right configutation in eth_defines. mohor 6466d 00h /ethmac/tags/rel_11/bench/
36 TX_BD_NUM register added instead of the RB_BD_ADDR. mohor 6526d 02h /ethmac/tags/rel_11/bench/
23 Number of addresses (wb_adr_i) minimized. mohor 6576d 03h /ethmac/tags/rel_11/bench/
22 eth_timescale.v changed to timescale.v This is done because of the
simulation of the few cores in a one joined project.
mohor 6576d 06h /ethmac/tags/rel_11/bench/
19 Defines changed (All precede with ETH_). Small changes because some
tools generate warnings when two operands are together. Synchronization
between two clocks domains in eth_wishbonedma.v is changed (due to ASIC
demands).
mohor 6601d 00h /ethmac/tags/rel_11/bench/
17 Signal names changed on the top level for easier pad insertion (ASIC). mohor 6641d 01h /ethmac/tags/rel_11/bench/
15 A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
Include files fixed to contain no path.
File names and module names changed ta have a eth_ prologue in the name.
File eth_timescale.v is used to define timescale
All pin names on the top module are changed to contain _I, _O or _OE at the end.
Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
and Mdo_OE. The bidirectional signal must be created on the top level. This
is done due to the ASIC tools.
mohor 6650d 00h /ethmac/tags/rel_11/bench/
12 Directory structure changed. Files checked and joind together. mohor 6656d 17h /ethmac/tags/rel_11/bench/

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