OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [tags/] [rel_11/] [bench/] [verilog/] - Rev 249

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
249 This commit was manufactured by cvs2svn to create tag 'rel_11'. 7851d 21h /ethmac/tags/rel_11/bench/verilog/
243 Late collision is not reported any more. tadejm 7856d 02h /ethmac/tags/rel_11/bench/verilog/
227 Changed BIST scan signals. tadejm 7882d 22h /ethmac/tags/rel_11/bench/verilog/
223 Some code changed due to bug fixes. tadejm 7883d 01h /ethmac/tags/rel_11/bench/verilog/
216 Bist signals added. mohor 7890d 01h /ethmac/tags/rel_11/bench/verilog/
209 Just back-up; not completed testbench and some testcases are not
wotking properly yet.		 tadejm 7892d 02h /ethmac/tags/rel_11/bench/verilog/
194 Full duplex tests modified and testbench bug repaired. tadej 7911d 00h /ethmac/tags/rel_11/bench/verilog/
192 Some additional reports added tadej 7912d 21h /ethmac/tags/rel_11/bench/verilog/
191 Bug repaired in eth_phy device tadej 7912d 21h /ethmac/tags/rel_11/bench/verilog/
189 Simple testbench that includes eth_cop, eth_host and eth_memory modules.
This testbench is used for testing the whole environment. Use tb_ethernet
testbench for testing just the ethernet MAC core (many tests).		 mohor 7912d 22h /ethmac/tags/rel_11/bench/verilog/
188 PHY changed. tadej 7913d 19h /ethmac/tags/rel_11/bench/verilog/
182 Full duplex test improved. tadej 7914d 21h /ethmac/tags/rel_11/bench/verilog/
181 MIIM test look better. mohor 7915d 00h /ethmac/tags/rel_11/bench/verilog/
180 Bench outputs data to display every 128 bytes. mohor 7917d 19h /ethmac/tags/rel_11/bench/verilog/
179 Beautiful tests merget together mohor 7917d 20h /ethmac/tags/rel_11/bench/verilog/
178 Rearanged testcases mohor 7917d 20h /ethmac/tags/rel_11/bench/verilog/
177 Bug in MIIM fixed. mohor 7918d 00h /ethmac/tags/rel_11/bench/verilog/
170 Headers changed. mohor 7918d 02h /ethmac/tags/rel_11/bench/verilog/
169 New testbench. Thanks to Tadej M - "The Spammer". mohor 7918d 03h /ethmac/tags/rel_11/bench/verilog/
158 Typo fixed. mohor 7922d 23h /ethmac/tags/rel_11/bench/verilog/
157 This testbench will soon be obsolete. Please use tb_ethernet.v mohor 7925d 04h /ethmac/tags/rel_11/bench/verilog/
156 Valid testbench. mohor 7925d 04h /ethmac/tags/rel_11/bench/verilog/
155 Minor changes. mohor 7925d 04h /ethmac/tags/rel_11/bench/verilog/
124 Define ETH_MIIMODER_RST corrected to 0x00000400. mohor 7967d 21h /ethmac/tags/rel_11/bench/verilog/
121 gsr added for use when ETH_XILINX_RAMB4 define is set. mohor 7969d 22h /ethmac/tags/rel_11/bench/verilog/
117 Clock mrx_clk set to 2.5 MHz. mohor 7974d 01h /ethmac/tags/rel_11/bench/verilog/
116 Testing environment also includes traffic cop, memory interface and host
interface.		 mohor 7974d 01h /ethmac/tags/rel_11/bench/verilog/
108 Testbench supports unaligned accesses. mohor 8051d 04h /ethmac/tags/rel_11/bench/verilog/
107 TX_BUF_BASE changed. mohor 8051d 04h /ethmac/tags/rel_11/bench/verilog/
92 Some defines that are used in testbench only were moved to tb_eth_defines.v
file.		 mohor 8096d 02h /ethmac/tags/rel_11/bench/verilog/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.