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[/] [ethmac/] [tags/] [rel_11/] [bench/] [verilog/] [tb_ethernet.v] - Rev 223

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223 Some code changed due to bug fixes. tadejm 7862d 10h /ethmac/tags/rel_11/bench/verilog/tb_ethernet.v
209 Just back-up; not completed testbench and some testcases are not
wotking properly yet.		 tadejm 7871d 10h /ethmac/tags/rel_11/bench/verilog/tb_ethernet.v
194 Full duplex tests modified and testbench bug repaired. tadej 7890d 09h /ethmac/tags/rel_11/bench/verilog/tb_ethernet.v
192 Some additional reports added tadej 7892d 06h /ethmac/tags/rel_11/bench/verilog/tb_ethernet.v
182 Full duplex test improved. tadej 7894d 06h /ethmac/tags/rel_11/bench/verilog/tb_ethernet.v
181 MIIM test look better. mohor 7894d 09h /ethmac/tags/rel_11/bench/verilog/tb_ethernet.v
180 Bench outputs data to display every 128 bytes. mohor 7897d 04h /ethmac/tags/rel_11/bench/verilog/tb_ethernet.v
179 Beautiful tests merget together mohor 7897d 05h /ethmac/tags/rel_11/bench/verilog/tb_ethernet.v
178 Rearanged testcases mohor 7897d 05h /ethmac/tags/rel_11/bench/verilog/tb_ethernet.v
177 Bug in MIIM fixed. mohor 7897d 09h /ethmac/tags/rel_11/bench/verilog/tb_ethernet.v
170 Headers changed. mohor 7897d 11h /ethmac/tags/rel_11/bench/verilog/tb_ethernet.v
169 New testbench. Thanks to Tadej M - "The Spammer". mohor 7897d 12h /ethmac/tags/rel_11/bench/verilog/tb_ethernet.v
158 Typo fixed. mohor 7902d 08h /ethmac/tags/rel_11/bench/verilog/tb_ethernet.v
156 Valid testbench. mohor 7904d 13h /ethmac/tags/rel_11/bench/verilog/tb_ethernet.v
121 gsr added for use when ETH_XILINX_RAMB4 define is set. mohor 7949d 07h /ethmac/tags/rel_11/bench/verilog/tb_ethernet.v
117 Clock mrx_clk set to 2.5 MHz. mohor 7953d 10h /ethmac/tags/rel_11/bench/verilog/tb_ethernet.v
116 Testing environment also includes traffic cop, memory interface and host
interface.		 mohor 7953d 10h /ethmac/tags/rel_11/bench/verilog/tb_ethernet.v

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