OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [tags/] [rel_11/] [rtl/] - Rev 239

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
239 RxError is not generated when small frame reception is enabled and small
frames are received.
tadejm 7853d 20h /ethmac/tags/rel_11/rtl
238 Defines fixed to use generic RAM by default. mohor 7866d 00h /ethmac/tags/rel_11/rtl
236 State machine goes from idle to the defer state when CarrierSense is 1. FCS (CRC appending) fixed to check the CrcEn bit also when padding is necessery. mohor 7868d 06h /ethmac/tags/rel_11/rtl
232 fpga define added. mohor 7874d 00h /ethmac/tags/rel_11/rtl
229 case changed to casex. mohor 7879d 22h /ethmac/tags/rel_11/rtl
227 Changed BIST scan signals. tadejm 7880d 01h /ethmac/tags/rel_11/rtl
226 Igor added WB burst support and repaired BUG when handling TX under-run and retry. tadejm 7880d 03h /ethmac/tags/rel_11/rtl
221 TxStatus is written after last access to the TX fifo is finished (in case of abort
or retry). TxDone is fixed.
mohor 7884d 02h /ethmac/tags/rel_11/rtl
219 txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,
TxDone and TxRetry are generated after the current WISHBONE access is
finished.
mohor 7887d 03h /ethmac/tags/rel_11/rtl
218 Typo error fixed. (When using Bist) mohor 7887d 05h /ethmac/tags/rel_11/rtl
214 Signals for WISHBONE B3 compliant interface added. mohor 7888d 02h /ethmac/tags/rel_11/rtl
213 Defines changed to have ETH_ prolog.
ETH_WISHBONE_B# define added.
mohor 7888d 02h /ethmac/tags/rel_11/rtl
212 Minor $display change. mohor 7888d 02h /ethmac/tags/rel_11/rtl
211 Bist added. mohor 7888d 02h /ethmac/tags/rel_11/rtl
210 BIST added. mohor 7888d 02h /ethmac/tags/rel_11/rtl
204 ETH_VIRTUAL_SILICON_RAM supported (for ASIC implementation). mohor 7905d 00h /ethmac/tags/rel_11/rtl
203 Virtual Silicon RAM might be used in the ASIC implementation of the ethernet
core.
mohor 7905d 00h /ethmac/tags/rel_11/rtl
202 CsMiss added. When address between 0x800 and 0xfff is accessed within
Ethernet Core, error acknowledge is generated.
mohor 7908d 01h /ethmac/tags/rel_11/rtl
168 CarrierSenseLost bug fixed when operating in full duplex mode. mohor 7916d 04h /ethmac/tags/rel_11/rtl
167 Sometimes both RxB_IRQ and RxE_IRQ were activated. Bug fixed. mohor 7917d 04h /ethmac/tags/rel_11/rtl
166 Reception is possible after RxPointer is read and not after BD is read. For
that reason RxBDReady is changed to RxReady.
Busy_IRQ interrupt connected. When there is no RxBD ready and frame
comes, interrupt is generated.
mohor 7918d 05h /ethmac/tags/rel_11/rtl
165 HASH improvement needed. mohor 7918d 08h /ethmac/tags/rel_11/rtl
164 Ethernet debug registers removed. mohor 7918d 08h /ethmac/tags/rel_11/rtl
161 Error acknowledge is generated when accessing BDs and RST bit in the
MODER register (r_Rst) is set.
mohor 7919d 05h /ethmac/tags/rel_11/rtl
160 error acknowledge cycle termination added to display. mohor 7919d 06h /ethmac/tags/rel_11/rtl
159 Async reset for WB_ACK_O removed (when core was in reset, it was
impossible to access BDs).
RxPointers and TxPointers names changed to be more descriptive.
TxUnderRun synchronized.
mohor 7920d 02h /ethmac/tags/rel_11/rtl
150 Debug registers reg1, 2, 3, 4 connected. Synchronization of many signals
changed (bugs fixed). Access to un-alligned buffers fixed. RxAbort signal
was not used OK.
mohor 7924d 00h /ethmac/tags/rel_11/rtl
149 Signals related to the control frames connected. Debug registers reg1, 2, 3, 4
connected.
mohor 7924d 00h /ethmac/tags/rel_11/rtl
148 Bug when last byte of destination address was not checked fixed. mohor 7924d 00h /ethmac/tags/rel_11/rtl
147 ETH_TXCTRL and ETH_RXCTRL registers added. Interrupts related to
the control frames connected.
mohor 7924d 00h /ethmac/tags/rel_11/rtl

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.