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[/] [ethmac/] [tags/] [rel_11/] [rtl/] [verilog/] [eth_registers.v] - Rev 338

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338 root 5469d 11h /ethmac/tags/rel_11/rtl/verilog/eth_registers.v
335 New directory structure. root 5526d 17h /ethmac/tags/rel_11/rtl/verilog/eth_registers.v
249 This commit was manufactured by cvs2svn to create tag 'rel_11'. 7829d 09h /ethmac/tags/rel_11/rtl/verilog/eth_registers.v
244 r_Rst signal does not reset any module any more and is removed from the design. mohor 7833d 08h /ethmac/tags/rel_11/rtl/verilog/eth_registers.v
164 Ethernet debug registers removed. mohor 7898d 16h /ethmac/tags/rel_11/rtl/verilog/eth_registers.v
147 ETH_TXCTRL and ETH_RXCTRL registers added. Interrupts related to
the control frames connected.		 mohor 7904d 08h /ethmac/tags/rel_11/rtl/verilog/eth_registers.v
143 Only values smaller or equal to 0x80 can be written to TX_BD_NUM register.
r_TxEn and r_RxEn depend on the limit values of the TX_BD_NUMOut.		 mohor 7920d 11h /ethmac/tags/rel_11/rtl/verilog/eth_registers.v
141 Syntax error fixed. mohor 7923d 04h /ethmac/tags/rel_11/rtl/verilog/eth_registers.v
140 Syntax error fixed. mohor 7923d 04h /ethmac/tags/rel_11/rtl/verilog/eth_registers.v
139 Synchronous reset added to all registers. Defines used for width. r_MiiMRst
changed from bit position 10 to 9.		 mohor 7923d 04h /ethmac/tags/rel_11/rtl/verilog/eth_registers.v
132 LinkFailRegister is reflecting the status of the PHY's link fail status bit. mohor 7925d 08h /ethmac/tags/rel_11/rtl/verilog/eth_registers.v
102 Interrupts are visible in the ETH_INT_SOURCE regardless if they are enabled
or not.		 mohor 8039d 13h /ethmac/tags/rel_11/rtl/verilog/eth_registers.v
74 Reset values are passed to registers through parameters mohor 8094d 10h /ethmac/tags/rel_11/rtl/verilog/eth_registers.v
69 Define missmatch fixed. mohor 8103d 13h /ethmac/tags/rel_11/rtl/verilog/eth_registers.v
68 Registered trimmed. Unused registers removed. mohor 8104d 13h /ethmac/tags/rel_11/rtl/verilog/eth_registers.v
56 File format fixed a bit. mohor 8105d 16h /ethmac/tags/rel_11/rtl/verilog/eth_registers.v
52 Modified for Address Checking,
addition of eth_addrcheck.v		 billditt 8106d 06h /ethmac/tags/rel_11/rtl/verilog/eth_registers.v
46 HASH0 and HASH1 registers added. mohor 8108d 10h /ethmac/tags/rel_11/rtl/verilog/eth_registers.v
37 Link in the header changed. mohor 8128d 16h /ethmac/tags/rel_11/rtl/verilog/eth_registers.v
34 RX_BD_NUM changed to TX_BD_NUM (holds number of TX descriptors
instead of the number of RX descriptors).		 mohor 8177d 12h /ethmac/tags/rel_11/rtl/verilog/eth_registers.v

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