OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [tags/] [rel_11/] [rtl/] [verilog/] [eth_top.v] - Rev 338

Rev

Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
80 Small fixes for external/internal DMA missmatches. mohor 8103d 05h /ethmac/tags/rel_11/rtl/verilog/eth_top.v
76 Interrupts changed in the top file mohor 8103d 06h /ethmac/tags/rel_11/rtl/verilog/eth_top.v
70 Small fixes. mohor 8111d 12h /ethmac/tags/rel_11/rtl/verilog/eth_top.v
68 Registered trimmed. Unused registers removed. mohor 8113d 08h /ethmac/tags/rel_11/rtl/verilog/eth_top.v
67 EXTERNAL_DMA used instead of WISHBONE_DMA. mohor 8113d 09h /ethmac/tags/rel_11/rtl/verilog/eth_top.v
65 Testbench fixed, code simplified, unused signals removed. mohor 8113d 15h /ethmac/tags/rel_11/rtl/verilog/eth_top.v
63 RxAbort is connected differently. mohor 8114d 09h /ethmac/tags/rel_11/rtl/verilog/eth_top.v
59 Changes that were lost when updating from 1.11 to 1.14 fixed. mohor 8114d 11h /ethmac/tags/rel_11/rtl/verilog/eth_top.v
52 Modified for Address Checking,
addition of eth_addrcheck.v
billditt 8115d 02h /ethmac/tags/rel_11/rtl/verilog/eth_top.v
47 HASH0 and HASH1 registers added. Registers address width was
changed to 8 bits.
mohor 8117d 05h /ethmac/tags/rel_11/rtl/verilog/eth_top.v

< Prev 1 2

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.