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Rev Log message Author Age Path
238 Defines fixed to use generic RAM by default. mohor 7138d 18h /ethmac/tags/rel_12/
236 State machine goes from idle to the defer state when CarrierSense is 1. FCS (CRC appending) fixed to check the CrcEn bit also when padding is necessery. mohor 7140d 23h /ethmac/tags/rel_12/
235 rev 4. mohor 7141d 14h /ethmac/tags/rel_12/
234 Figure list assed to the revision 3. mohor 7141d 22h /ethmac/tags/rel_12/
233 Revision 0.3 released. Some figures added. mohor 7141d 23h /ethmac/tags/rel_12/
232 fpga define added. mohor 7146d 18h /ethmac/tags/rel_12/
231 Description of Core Modules added (figure). mohor 7148d 19h /ethmac/tags/rel_12/
229 case changed to casex. mohor 7152d 15h /ethmac/tags/rel_12/
227 Changed BIST scan signals. tadejm 7152d 19h /ethmac/tags/rel_12/
226 Igor added WB burst support and repaired BUG when handling TX under-run and retry. tadejm 7152d 21h /ethmac/tags/rel_12/
225 Some minor changes. tadejm 7152d 21h /ethmac/tags/rel_12/
224 Signals for a wave window in Modelsim. tadejm 7152d 22h /ethmac/tags/rel_12/
223 Some code changed due to bug fixes. tadejm 7152d 22h /ethmac/tags/rel_12/
221 TxStatus is written after last access to the TX fifo is finished (in case of abort
or retry). TxDone is fixed.
mohor 7156d 20h /ethmac/tags/rel_12/
219 txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,
TxDone and TxRetry are generated after the current WISHBONE access is
finished.
mohor 7159d 21h /ethmac/tags/rel_12/
218 Typo error fixed. (When using Bist) mohor 7159d 23h /ethmac/tags/rel_12/
217 Bist supported. mohor 7159d 23h /ethmac/tags/rel_12/
216 Bist signals added. mohor 7159d 23h /ethmac/tags/rel_12/
215 Bist supported. mohor 7160d 00h /ethmac/tags/rel_12/
214 Signals for WISHBONE B3 compliant interface added. mohor 7160d 20h /ethmac/tags/rel_12/

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