Subversion Repositories ethmac

[/] [ethmac/] [tags/] [rel_12/] - Rev 239


Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
239 RxError is not generated when small frame reception is enabled and small
frames are received.
tadejm 7130d 09h /ethmac/tags/rel_12/
238 Defines fixed to use generic RAM by default. mohor 7142d 13h /ethmac/tags/rel_12/
236 State machine goes from idle to the defer state when CarrierSense is 1. FCS (CRC appending) fixed to check the CrcEn bit also when padding is necessery. mohor 7144d 19h /ethmac/tags/rel_12/
235 rev 4. mohor 7145d 09h /ethmac/tags/rel_12/
234 Figure list assed to the revision 3. mohor 7145d 18h /ethmac/tags/rel_12/
233 Revision 0.3 released. Some figures added. mohor 7145d 18h /ethmac/tags/rel_12/
232 fpga define added. mohor 7150d 13h /ethmac/tags/rel_12/
231 Description of Core Modules added (figure). mohor 7152d 14h /ethmac/tags/rel_12/
229 case changed to casex. mohor 7156d 11h /ethmac/tags/rel_12/
227 Changed BIST scan signals. tadejm 7156d 15h /ethmac/tags/rel_12/
226 Igor added WB burst support and repaired BUG when handling TX under-run and retry. tadejm 7156d 16h /ethmac/tags/rel_12/
225 Some minor changes. tadejm 7156d 16h /ethmac/tags/rel_12/
224 Signals for a wave window in Modelsim. tadejm 7156d 18h /ethmac/tags/rel_12/
223 Some code changed due to bug fixes. tadejm 7156d 18h /ethmac/tags/rel_12/
221 TxStatus is written after last access to the TX fifo is finished (in case of abort
or retry). TxDone is fixed.
mohor 7160d 16h /ethmac/tags/rel_12/
219 txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,
TxDone and TxRetry are generated after the current WISHBONE access is
mohor 7163d 16h /ethmac/tags/rel_12/
218 Typo error fixed. (When using Bist) mohor 7163d 18h /ethmac/tags/rel_12/
217 Bist supported. mohor 7163d 18h /ethmac/tags/rel_12/
216 Bist signals added. mohor 7163d 18h /ethmac/tags/rel_12/
215 Bist supported. mohor 7163d 19h /ethmac/tags/rel_12/
214 Signals for WISHBONE B3 compliant interface added. mohor 7164d 15h /ethmac/tags/rel_12/
213 Defines changed to have ETH_ prolog.
ETH_WISHBONE_B# define added.
mohor 7164d 15h /ethmac/tags/rel_12/
212 Minor $display change. mohor 7164d 15h /ethmac/tags/rel_12/
211 Bist added. mohor 7164d 15h /ethmac/tags/rel_12/
210 BIST added. mohor 7164d 15h /ethmac/tags/rel_12/
209 Just back-up; not completed testbench and some testcases are not
wotking properly yet.
tadejm 7165d 18h /ethmac/tags/rel_12/
208 Virtual Silicon RAMs moved to lib directory tadej 7181d 12h /ethmac/tags/rel_12/
207 Virtual Silicon RAM support fixed tadej 7181d 13h /ethmac/tags/rel_12/
206 Virtual Silicon RAM added to the simulation. mohor 7181d 13h /ethmac/tags/rel_12/
205 ETH_VIRTUAL_SILICON_RAM supported. mohor 7181d 13h /ethmac/tags/rel_12/

powered by: WebSVN 2.1.0

© copyright 1999-2022, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.