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338 root 3847d 16h /ethmac/tags/rel_12/
335 New directory structure. root 3904d 22h /ethmac/tags/rel_12/
258 This commit was manufactured by cvs2svn to create tag 'rel_12'. 6205d 07h /ethmac/tags/rel_12/
257 When TxUsedData and CtrlMux occur at the same time, byte counter needs
to be incremented by 2. Signal IncrementByteCntBy2 added for that reason.
mohor 6205d 07h /ethmac/tags/rel_12/
256 TxDone and TxAbort changed so they're not propagated to the wishbone
module when control frame is transmitted.
mohor 6205d 07h /ethmac/tags/rel_12/
255 TPauseRq synchronized to tx_clk. mohor 6205d 08h /ethmac/tags/rel_12/
254 Temp version. mohor 6206d 11h /ethmac/tags/rel_12/
253 r_MiiMRst is not used for resetting the MIIM module. wb_rst used instead. mohor 6206d 14h /ethmac/tags/rel_12/
252 Just some updates. tadejm 6206d 14h /ethmac/tags/rel_12/
251 When control frame (PAUSE) was sent, status was written in the
eth_wishbone module and both TXB and TXC interrupts were set. Fixed.
Only TXC interrupt is set.
mohor 6206d 14h /ethmac/tags/rel_12/
250 AddressMiss status is connecting to the Rx BD. AddressMiss is identifying
that a frame was received because of the promiscous mode.
mohor 6206d 14h /ethmac/tags/rel_12/
248 wb_rst_i is used for MIIM reset. mohor 6207d 14h /ethmac/tags/rel_12/
246 Since r_Rst bit is not used any more, default value is changed to 0xa000. mohor 6210d 17h /ethmac/tags/rel_12/
245 Rev 1.7. mohor 6211d 11h /ethmac/tags/rel_12/
244 r_Rst signal does not reset any module any more and is removed from the design. mohor 6211d 13h /ethmac/tags/rel_12/
243 Late collision is not reported any more. tadejm 6211d 19h /ethmac/tags/rel_12/
242 Late collision is reported only when not in the full duplex.
Sample is taken (for status) as soon as MRxDV is not valid (regardless
of the received byte cnt).
tadejm 6212d 09h /ethmac/tags/rel_12/
241 StartIdle state changed (not important the size of the packet).
StartData1 activates only while ByteCnt is smaller than the MaxFrame.
tadejm 6212d 09h /ethmac/tags/rel_12/
240 All modules are reset with wb_rst instead of the r_Rst. Exception is MII module. tadejm 6212d 09h /ethmac/tags/rel_12/
239 RxError is not generated when small frame reception is enabled and small
frames are received.
tadejm 6212d 09h /ethmac/tags/rel_12/
238 Defines fixed to use generic RAM by default. mohor 6224d 13h /ethmac/tags/rel_12/
236 State machine goes from idle to the defer state when CarrierSense is 1. FCS (CRC appending) fixed to check the CrcEn bit also when padding is necessery. mohor 6226d 19h /ethmac/tags/rel_12/
235 rev 4. mohor 6227d 09h /ethmac/tags/rel_12/
234 Figure list assed to the revision 3. mohor 6227d 18h /ethmac/tags/rel_12/
233 Revision 0.3 released. Some figures added. mohor 6227d 18h /ethmac/tags/rel_12/
232 fpga define added. mohor 6232d 13h /ethmac/tags/rel_12/
231 Description of Core Modules added (figure). mohor 6234d 14h /ethmac/tags/rel_12/
229 case changed to casex. mohor 6238d 11h /ethmac/tags/rel_12/
227 Changed BIST scan signals. tadejm 6238d 15h /ethmac/tags/rel_12/
226 Igor added WB burst support and repaired BUG when handling TX under-run and retry. tadejm 6238d 16h /ethmac/tags/rel_12/

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