OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [tags/] [rel_12/] [rtl/] [verilog/] - Rev 244

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
244 r_Rst signal does not reset any module any more and is removed from the design. mohor 7846d 22h /ethmac/tags/rel_12/rtl/verilog/
242 Late collision is reported only when not in the full duplex.
Sample is taken (for status) as soon as MRxDV is not valid (regardless
of the received byte cnt).		 tadejm 7847d 18h /ethmac/tags/rel_12/rtl/verilog/
241 StartIdle state changed (not important the size of the packet).
StartData1 activates only while ByteCnt is smaller than the MaxFrame.		 tadejm 7847d 18h /ethmac/tags/rel_12/rtl/verilog/
240 All modules are reset with wb_rst instead of the r_Rst. Exception is MII module. tadejm 7847d 18h /ethmac/tags/rel_12/rtl/verilog/
239 RxError is not generated when small frame reception is enabled and small
frames are received.		 tadejm 7847d 18h /ethmac/tags/rel_12/rtl/verilog/
238 Defines fixed to use generic RAM by default. mohor 7859d 22h /ethmac/tags/rel_12/rtl/verilog/
236 State machine goes from idle to the defer state when CarrierSense is 1. FCS (CRC appending) fixed to check the CrcEn bit also when padding is necessery. mohor 7862d 04h /ethmac/tags/rel_12/rtl/verilog/
232 fpga define added. mohor 7867d 22h /ethmac/tags/rel_12/rtl/verilog/
229 case changed to casex. mohor 7873d 20h /ethmac/tags/rel_12/rtl/verilog/
227 Changed BIST scan signals. tadejm 7874d 00h /ethmac/tags/rel_12/rtl/verilog/
226 Igor added WB burst support and repaired BUG when handling TX under-run and retry. tadejm 7874d 01h /ethmac/tags/rel_12/rtl/verilog/
221 TxStatus is written after last access to the TX fifo is finished (in case of abort
or retry). TxDone is fixed.		 mohor 7878d 00h /ethmac/tags/rel_12/rtl/verilog/
219 txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,
TxDone and TxRetry are generated after the current WISHBONE access is
finished.		 mohor 7881d 01h /ethmac/tags/rel_12/rtl/verilog/
218 Typo error fixed. (When using Bist) mohor 7881d 03h /ethmac/tags/rel_12/rtl/verilog/
214 Signals for WISHBONE B3 compliant interface added. mohor 7882d 00h /ethmac/tags/rel_12/rtl/verilog/
213 Defines changed to have ETH_ prolog.
ETH_WISHBONE_B# define added.		 mohor 7882d 00h /ethmac/tags/rel_12/rtl/verilog/
212 Minor $display change. mohor 7882d 00h /ethmac/tags/rel_12/rtl/verilog/
211 Bist added. mohor 7882d 00h /ethmac/tags/rel_12/rtl/verilog/
210 BIST added. mohor 7882d 00h /ethmac/tags/rel_12/rtl/verilog/
204 ETH_VIRTUAL_SILICON_RAM supported (for ASIC implementation). mohor 7898d 22h /ethmac/tags/rel_12/rtl/verilog/
203 Virtual Silicon RAM might be used in the ASIC implementation of the ethernet
core.		 mohor 7898d 22h /ethmac/tags/rel_12/rtl/verilog/
202 CsMiss added. When address between 0x800 and 0xfff is accessed within
Ethernet Core, error acknowledge is generated.		 mohor 7901d 23h /ethmac/tags/rel_12/rtl/verilog/
168 CarrierSenseLost bug fixed when operating in full duplex mode. mohor 7910d 02h /ethmac/tags/rel_12/rtl/verilog/
167 Sometimes both RxB_IRQ and RxE_IRQ were activated. Bug fixed. mohor 7911d 02h /ethmac/tags/rel_12/rtl/verilog/
166 Reception is possible after RxPointer is read and not after BD is read. For
that reason RxBDReady is changed to RxReady.
Busy_IRQ interrupt connected. When there is no RxBD ready and frame
comes, interrupt is generated.		 mohor 7912d 03h /ethmac/tags/rel_12/rtl/verilog/
165 HASH improvement needed. mohor 7912d 06h /ethmac/tags/rel_12/rtl/verilog/
164 Ethernet debug registers removed. mohor 7912d 06h /ethmac/tags/rel_12/rtl/verilog/
161 Error acknowledge is generated when accessing BDs and RST bit in the
MODER register (r_Rst) is set.		 mohor 7913d 04h /ethmac/tags/rel_12/rtl/verilog/
160 error acknowledge cycle termination added to display. mohor 7913d 04h /ethmac/tags/rel_12/rtl/verilog/
159 Async reset for WB_ACK_O removed (when core was in reset, it was
impossible to access BDs).
RxPointers and TxPointers names changed to be more descriptive.
TxUnderRun synchronized.		 mohor 7914d 00h /ethmac/tags/rel_12/rtl/verilog/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.