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[/] [ethmac/] [tags/] [rel_12/] [rtl/] [verilog/] [eth_defines.v] - Rev 338

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338 root 5475d 10h /ethmac/tags/rel_12/rtl/verilog/eth_defines.v
335 New directory structure. root 5532d 15h /ethmac/tags/rel_12/rtl/verilog/eth_defines.v
258 This commit was manufactured by cvs2svn to create tag 'rel_12'. 7833d 01h /ethmac/tags/rel_12/rtl/verilog/eth_defines.v
253 r_MiiMRst is not used for resetting the MIIM module. wb_rst used instead. mohor 7834d 07h /ethmac/tags/rel_12/rtl/verilog/eth_defines.v
246 Since r_Rst bit is not used any more, default value is changed to 0xa000. mohor 7838d 10h /ethmac/tags/rel_12/rtl/verilog/eth_defines.v
238 Defines fixed to use generic RAM by default. mohor 7852d 07h /ethmac/tags/rel_12/rtl/verilog/eth_defines.v
232 fpga define added. mohor 7860d 06h /ethmac/tags/rel_12/rtl/verilog/eth_defines.v
213 Defines changed to have ETH_ prolog.
ETH_WISHBONE_B# define added.		 mohor 7874d 08h /ethmac/tags/rel_12/rtl/verilog/eth_defines.v
211 Bist added. mohor 7874d 08h /ethmac/tags/rel_12/rtl/verilog/eth_defines.v
203 Virtual Silicon RAM might be used in the ASIC implementation of the ethernet
core.		 mohor 7891d 07h /ethmac/tags/rel_12/rtl/verilog/eth_defines.v
145 Defines for control registers added (ETH_TXCTRL and ETH_RXCTRL). mohor 7910d 06h /ethmac/tags/rel_12/rtl/verilog/eth_defines.v
137 Defines for register width added. mii_rst signal in MIIMODER register
changed.		 mohor 7929d 03h /ethmac/tags/rel_12/rtl/verilog/eth_defines.v
134 Register TX_BD_NUM is changed so it contains value of the Tx buffer descriptors. No
need to multiply or devide any more.		 mohor 7931d 05h /ethmac/tags/rel_12/rtl/verilog/eth_defines.v
119 Ram , used for BDs changed from generic_spram to eth_spram_256x32. mohor 7953d 09h /ethmac/tags/rel_12/rtl/verilog/eth_defines.v
106 Outputs registered. Reset changed for eth_wishbone module. mohor 8034d 15h /ethmac/tags/rel_12/rtl/verilog/eth_defines.v
105 Compiler directives added. Tx and Rx fifo size incremented. A "late collision"
bug fixed.		 mohor 8043d 16h /ethmac/tags/rel_12/rtl/verilog/eth_defines.v
92 Some defines that are used in testbench only were moved to tb_eth_defines.v
file.		 mohor 8079d 12h /ethmac/tags/rel_12/rtl/verilog/eth_defines.v
73 Number of interrupts changed mohor 8100d 09h /ethmac/tags/rel_12/rtl/verilog/eth_defines.v
68 Registered trimmed. Unused registers removed. mohor 8110d 11h /ethmac/tags/rel_12/rtl/verilog/eth_defines.v
67 EXTERNAL_DMA used instead of WISHBONE_DMA. mohor 8110d 12h /ethmac/tags/rel_12/rtl/verilog/eth_defines.v
55 Changed that were lost with last update put back to the file. mohor 8111d 14h /ethmac/tags/rel_12/rtl/verilog/eth_defines.v
52 Modified for Address Checking,
addition of eth_addrcheck.v		 billditt 8112d 05h /ethmac/tags/rel_12/rtl/verilog/eth_defines.v
46 HASH0 and HASH1 registers added. mohor 8114d 08h /ethmac/tags/rel_12/rtl/verilog/eth_defines.v
42 Rx status is written back to the BD. mohor 8118d 09h /ethmac/tags/rel_12/rtl/verilog/eth_defines.v
40 Both rx and tx part are finished. Tested with wb_clk_i between 10 and 200
MHz. Statuses, overrun, control frame transmission and reception still need
to be fixed.		 mohor 8121d 08h /ethmac/tags/rel_12/rtl/verilog/eth_defines.v
37 Link in the header changed. mohor 8134d 14h /ethmac/tags/rel_12/rtl/verilog/eth_defines.v
34 RX_BD_NUM changed to TX_BD_NUM (holds number of TX descriptors
instead of the number of RX descriptors).		 mohor 8183d 10h /ethmac/tags/rel_12/rtl/verilog/eth_defines.v
32 ETH_RX_BD_ADR register deleted. ETH_RX_BD_NUM is used instead. mohor 8183d 15h /ethmac/tags/rel_12/rtl/verilog/eth_defines.v
29 Generic memory model is used. Defines are changed for the same reason. mohor 8205d 11h /ethmac/tags/rel_12/rtl/verilog/eth_defines.v
21 Status signals changed, Adress decoding changed, interrupt controller
added.		 mohor 8231d 13h /ethmac/tags/rel_12/rtl/verilog/eth_defines.v

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