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[/] [ethmac/] [tags/] [rel_12/] [rtl/] [verilog/] [eth_top.v] - Rev 202

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Rev	Log message	Author	Age	Path
202	CsMiss added. When address between 0x800 and 0xfff is accessed within Ethernet Core, error acknowledge is generated.	mohor	7905d 04h	/ethmac/tags/rel_12/rtl/verilog/eth_top.v
168	CarrierSenseLost bug fixed when operating in full duplex mode.	mohor	7913d 06h	/ethmac/tags/rel_12/rtl/verilog/eth_top.v
164	Ethernet debug registers removed.	mohor	7915d 10h	/ethmac/tags/rel_12/rtl/verilog/eth_top.v
161	Error acknowledge is generated when accessing BDs and RST bit in the MODER register (r_Rst) is set.	mohor	7916d 08h	/ethmac/tags/rel_12/rtl/verilog/eth_top.v
149	Signals related to the control frames connected. Debug registers reg1, 2, 3, 4 connected.	mohor	7921d 02h	/ethmac/tags/rel_12/rtl/verilog/eth_top.v
125	RxAbort changed. Packets received with MRxErr (from PHY) are also aborted.	mohor	7962d 03h	/ethmac/tags/rel_12/rtl/verilog/eth_top.v
114	EXTERNAL_DMA removed. External DMA not supported.	mohor	7970d 02h	/ethmac/tags/rel_12/rtl/verilog/eth_top.v
106	Outputs registered. Reset changed for eth_wishbone module.	mohor	8045d 11h	/ethmac/tags/rel_12/rtl/verilog/eth_top.v
103	Wishbone signals are registered when ETH_REGISTERED_OUTPUTS is selected in eth_defines.v	mohor	8056d 07h	/ethmac/tags/rel_12/rtl/verilog/eth_top.v
95	md_padoen_o changed to md_padoe_o. Signal was always active high, just name was incorrect.	mohor	8084d 07h	/ethmac/tags/rel_12/rtl/verilog/eth_top.v
80	Small fixes for external/internal DMA missmatches.	mohor	8111d 04h	/ethmac/tags/rel_12/rtl/verilog/eth_top.v
76	Interrupts changed in the top file	mohor	8111d 05h	/ethmac/tags/rel_12/rtl/verilog/eth_top.v
70	Small fixes.	mohor	8119d 10h	/ethmac/tags/rel_12/rtl/verilog/eth_top.v
68	Registered trimmed. Unused registers removed.	mohor	8121d 07h	/ethmac/tags/rel_12/rtl/verilog/eth_top.v
67	EXTERNAL_DMA used instead of WISHBONE_DMA.	mohor	8121d 08h	/ethmac/tags/rel_12/rtl/verilog/eth_top.v
65	Testbench fixed, code simplified, unused signals removed.	mohor	8121d 14h	/ethmac/tags/rel_12/rtl/verilog/eth_top.v
63	RxAbort is connected differently.	mohor	8122d 07h	/ethmac/tags/rel_12/rtl/verilog/eth_top.v
59	Changes that were lost when updating from 1.11 to 1.14 fixed.	mohor	8122d 09h	/ethmac/tags/rel_12/rtl/verilog/eth_top.v
52	Modified for Address Checking, addition of eth_addrcheck.v	billditt	8123d 01h	/ethmac/tags/rel_12/rtl/verilog/eth_top.v
47	HASH0 and HASH1 registers added. Registers address width was changed to 8 bits.	mohor	8125d 04h	/ethmac/tags/rel_12/rtl/verilog/eth_top.v

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[/] [ethmac/] [tags/] [rel_12/] [rtl/] [verilog/] [eth_top.v] - Rev 202

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