URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [tags/] [rel_12/] [rtl/] [verilog/] [eth_top.v] - Rev 258

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

From rev	To rev	Max revs

Search for

Rev	Log message	Author	Age	Path
258	This commit was manufactured by cvs2svn to create tag 'rel_12'.		7843d 04h	/ethmac/tags/rel_12/rtl/verilog/eth_top.v
255	TPauseRq synchronized to tx_clk.	mohor	7843d 05h	/ethmac/tags/rel_12/rtl/verilog/eth_top.v
253	r_MiiMRst is not used for resetting the MIIM module. wb_rst used instead.	mohor	7844d 10h	/ethmac/tags/rel_12/rtl/verilog/eth_top.v
250	AddressMiss status is connecting to the Rx BD. AddressMiss is identifying that a frame was received because of the promiscous mode.	mohor	7844d 11h	/ethmac/tags/rel_12/rtl/verilog/eth_top.v
248	wb_rst_i is used for MIIM reset.	mohor	7845d 11h	/ethmac/tags/rel_12/rtl/verilog/eth_top.v
244	r_Rst signal does not reset any module any more and is removed from the design.	mohor	7849d 10h	/ethmac/tags/rel_12/rtl/verilog/eth_top.v
240	All modules are reset with wb_rst instead of the r_Rst. Exception is MII module.	tadejm	7850d 06h	/ethmac/tags/rel_12/rtl/verilog/eth_top.v
227	Changed BIST scan signals.	tadejm	7876d 12h	/ethmac/tags/rel_12/rtl/verilog/eth_top.v
218	Typo error fixed. (When using Bist)	mohor	7883d 15h	/ethmac/tags/rel_12/rtl/verilog/eth_top.v
214	Signals for WISHBONE B3 compliant interface added.	mohor	7884d 12h	/ethmac/tags/rel_12/rtl/verilog/eth_top.v
210	BIST added.	mohor	7884d 12h	/ethmac/tags/rel_12/rtl/verilog/eth_top.v
202	CsMiss added. When address between 0x800 and 0xfff is accessed within Ethernet Core, error acknowledge is generated.	mohor	7904d 12h	/ethmac/tags/rel_12/rtl/verilog/eth_top.v
168	CarrierSenseLost bug fixed when operating in full duplex mode.	mohor	7912d 14h	/ethmac/tags/rel_12/rtl/verilog/eth_top.v
164	Ethernet debug registers removed.	mohor	7914d 18h	/ethmac/tags/rel_12/rtl/verilog/eth_top.v
161	Error acknowledge is generated when accessing BDs and RST bit in the MODER register (r_Rst) is set.	mohor	7915d 16h	/ethmac/tags/rel_12/rtl/verilog/eth_top.v
149	Signals related to the control frames connected. Debug registers reg1, 2, 3, 4 connected.	mohor	7920d 10h	/ethmac/tags/rel_12/rtl/verilog/eth_top.v
125	RxAbort changed. Packets received with MRxErr (from PHY) are also aborted.	mohor	7961d 10h	/ethmac/tags/rel_12/rtl/verilog/eth_top.v
114	EXTERNAL_DMA removed. External DMA not supported.	mohor	7969d 10h	/ethmac/tags/rel_12/rtl/verilog/eth_top.v
106	Outputs registered. Reset changed for eth_wishbone module.	mohor	8044d 18h	/ethmac/tags/rel_12/rtl/verilog/eth_top.v
103	Wishbone signals are registered when ETH_REGISTERED_OUTPUTS is selected in eth_defines.v	mohor	8055d 14h	/ethmac/tags/rel_12/rtl/verilog/eth_top.v

1 2 Next >

Show All

Browse

Tools

Subversion Repositories ethmac

[/] [ethmac/] [tags/] [rel_12/] [rtl/] [verilog/] [eth_top.v] - Rev 258

Filtering Options