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Rev Log message Author Age Path
221 TxStatus is written after last access to the TX fifo is finished (in case of abort
or retry). TxDone is fixed.		 mohor 7870d 13h /ethmac/tags/rel_13/
219 txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,
TxDone and TxRetry are generated after the current WISHBONE access is
finished.		 mohor 7873d 14h /ethmac/tags/rel_13/
218 Typo error fixed. (When using Bist) mohor 7873d 16h /ethmac/tags/rel_13/
217 Bist supported. mohor 7873d 16h /ethmac/tags/rel_13/
216 Bist signals added. mohor 7873d 16h /ethmac/tags/rel_13/
215 Bist supported. mohor 7873d 16h /ethmac/tags/rel_13/
214 Signals for WISHBONE B3 compliant interface added. mohor 7874d 12h /ethmac/tags/rel_13/
213 Defines changed to have ETH_ prolog.
ETH_WISHBONE_B# define added.		 mohor 7874d 12h /ethmac/tags/rel_13/
212 Minor $display change. mohor 7874d 12h /ethmac/tags/rel_13/
211 Bist added. mohor 7874d 13h /ethmac/tags/rel_13/
210 BIST added. mohor 7874d 13h /ethmac/tags/rel_13/
209 Just back-up; not completed testbench and some testcases are not
wotking properly yet.		 tadejm 7875d 16h /ethmac/tags/rel_13/
208 Virtual Silicon RAMs moved to lib directory tadej 7891d 10h /ethmac/tags/rel_13/
207 Virtual Silicon RAM support fixed tadej 7891d 10h /ethmac/tags/rel_13/
206 Virtual Silicon RAM added to the simulation. mohor 7891d 10h /ethmac/tags/rel_13/
205 ETH_VIRTUAL_SILICON_RAM supported. mohor 7891d 11h /ethmac/tags/rel_13/
204 ETH_VIRTUAL_SILICON_RAM supported (for ASIC implementation). mohor 7891d 11h /ethmac/tags/rel_13/
203 Virtual Silicon RAM might be used in the ASIC implementation of the ethernet
core.		 mohor 7891d 11h /ethmac/tags/rel_13/
202 CsMiss added. When address between 0x800 and 0xfff is accessed within
Ethernet Core, error acknowledge is generated.		 mohor 7894d 12h /ethmac/tags/rel_13/
201 Core size added to the document. mohor 7894d 13h /ethmac/tags/rel_13/

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