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252 Just some updates. tadejm 7123d 10h /ethmac/tags/rel_13/
251 When control frame (PAUSE) was sent, status was written in the
eth_wishbone module and both TXB and TXC interrupts were set. Fixed.
Only TXC interrupt is set.
mohor 7123d 10h /ethmac/tags/rel_13/
250 AddressMiss status is connecting to the Rx BD. AddressMiss is identifying
that a frame was received because of the promiscous mode.
mohor 7123d 10h /ethmac/tags/rel_13/
248 wb_rst_i is used for MIIM reset. mohor 7124d 10h /ethmac/tags/rel_13/
246 Since r_Rst bit is not used any more, default value is changed to 0xa000. mohor 7127d 13h /ethmac/tags/rel_13/
245 Rev 1.7. mohor 7128d 06h /ethmac/tags/rel_13/
244 r_Rst signal does not reset any module any more and is removed from the design. mohor 7128d 09h /ethmac/tags/rel_13/
243 Late collision is not reported any more. tadejm 7128d 14h /ethmac/tags/rel_13/
242 Late collision is reported only when not in the full duplex.
Sample is taken (for status) as soon as MRxDV is not valid (regardless
of the received byte cnt).
tadejm 7129d 05h /ethmac/tags/rel_13/
241 StartIdle state changed (not important the size of the packet).
StartData1 activates only while ByteCnt is smaller than the MaxFrame.
tadejm 7129d 05h /ethmac/tags/rel_13/
240 All modules are reset with wb_rst instead of the r_Rst. Exception is MII module. tadejm 7129d 05h /ethmac/tags/rel_13/
239 RxError is not generated when small frame reception is enabled and small
frames are received.
tadejm 7129d 05h /ethmac/tags/rel_13/
238 Defines fixed to use generic RAM by default. mohor 7141d 09h /ethmac/tags/rel_13/
236 State machine goes from idle to the defer state when CarrierSense is 1. FCS (CRC appending) fixed to check the CrcEn bit also when padding is necessery. mohor 7143d 14h /ethmac/tags/rel_13/
235 rev 4. mohor 7144d 05h /ethmac/tags/rel_13/
234 Figure list assed to the revision 3. mohor 7144d 13h /ethmac/tags/rel_13/
233 Revision 0.3 released. Some figures added. mohor 7144d 13h /ethmac/tags/rel_13/
232 fpga define added. mohor 7149d 08h /ethmac/tags/rel_13/
231 Description of Core Modules added (figure). mohor 7151d 10h /ethmac/tags/rel_13/
229 case changed to casex. mohor 7155d 06h /ethmac/tags/rel_13/
227 Changed BIST scan signals. tadejm 7155d 10h /ethmac/tags/rel_13/
226 Igor added WB burst support and repaired BUG when handling TX under-run and retry. tadejm 7155d 12h /ethmac/tags/rel_13/
225 Some minor changes. tadejm 7155d 12h /ethmac/tags/rel_13/
224 Signals for a wave window in Modelsim. tadejm 7155d 13h /ethmac/tags/rel_13/
223 Some code changed due to bug fixes. tadejm 7155d 13h /ethmac/tags/rel_13/
221 TxStatus is written after last access to the TX fifo is finished (in case of abort
or retry). TxDone is fixed.
mohor 7159d 11h /ethmac/tags/rel_13/
219 txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,
TxDone and TxRetry are generated after the current WISHBONE access is
finished.
mohor 7162d 12h /ethmac/tags/rel_13/
218 Typo error fixed. (When using Bist) mohor 7162d 14h /ethmac/tags/rel_13/
217 Bist supported. mohor 7162d 14h /ethmac/tags/rel_13/
216 Bist signals added. mohor 7162d 14h /ethmac/tags/rel_13/

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