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[/] [ethmac/] [tags/] [rel_13/] [rtl/] - Rev 345

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338 root 5489d 05h /ethmac/tags/rel_13/rtl/
335 New directory structure. root 5546d 10h /ethmac/tags/rel_13/rtl/
265 This commit was manufactured by cvs2svn to create tag 'rel_13'. 7845d 06h /ethmac/tags/rel_13/rtl/
264 Registers RxStatusWrite_rck and RxStatusWriteLatched were not used
anywhere. Removed.		 mohor 7845d 06h /ethmac/tags/rel_13/rtl/
261 Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
synchronized.		 mohor 7845d 18h /ethmac/tags/rel_13/rtl/
259 In loopback rx_clk is not looped back. Possible CRC error. Consider if usage
of additional logic is necessery (FIFO for looping the data).		 mohor 7846d 19h /ethmac/tags/rel_13/rtl/
257 When TxUsedData and CtrlMux occur at the same time, byte counter needs
to be incremented by 2. Signal IncrementByteCntBy2 added for that reason.		 mohor 7846d 20h /ethmac/tags/rel_13/rtl/
256 TxDone and TxAbort changed so they're not propagated to the wishbone
module when control frame is transmitted.		 mohor 7846d 20h /ethmac/tags/rel_13/rtl/
255 TPauseRq synchronized to tx_clk. mohor 7846d 20h /ethmac/tags/rel_13/rtl/
253 r_MiiMRst is not used for resetting the MIIM module. wb_rst used instead. mohor 7848d 02h /ethmac/tags/rel_13/rtl/
251 When control frame (PAUSE) was sent, status was written in the
eth_wishbone module and both TXB and TXC interrupts were set. Fixed.
Only TXC interrupt is set.		 mohor 7848d 02h /ethmac/tags/rel_13/rtl/
250 AddressMiss status is connecting to the Rx BD. AddressMiss is identifying
that a frame was received because of the promiscous mode.		 mohor 7848d 02h /ethmac/tags/rel_13/rtl/
248 wb_rst_i is used for MIIM reset. mohor 7849d 02h /ethmac/tags/rel_13/rtl/
246 Since r_Rst bit is not used any more, default value is changed to 0xa000. mohor 7852d 05h /ethmac/tags/rel_13/rtl/
244 r_Rst signal does not reset any module any more and is removed from the design. mohor 7853d 01h /ethmac/tags/rel_13/rtl/
242 Late collision is reported only when not in the full duplex.
Sample is taken (for status) as soon as MRxDV is not valid (regardless
of the received byte cnt).		 tadejm 7853d 21h /ethmac/tags/rel_13/rtl/
241 StartIdle state changed (not important the size of the packet).
StartData1 activates only while ByteCnt is smaller than the MaxFrame.		 tadejm 7853d 21h /ethmac/tags/rel_13/rtl/
240 All modules are reset with wb_rst instead of the r_Rst. Exception is MII module. tadejm 7853d 21h /ethmac/tags/rel_13/rtl/
239 RxError is not generated when small frame reception is enabled and small
frames are received.		 tadejm 7853d 22h /ethmac/tags/rel_13/rtl/
238 Defines fixed to use generic RAM by default. mohor 7866d 02h /ethmac/tags/rel_13/rtl/
236 State machine goes from idle to the defer state when CarrierSense is 1. FCS (CRC appending) fixed to check the CrcEn bit also when padding is necessery. mohor 7868d 07h /ethmac/tags/rel_13/rtl/
232 fpga define added. mohor 7874d 01h /ethmac/tags/rel_13/rtl/
229 case changed to casex. mohor 7879d 23h /ethmac/tags/rel_13/rtl/
227 Changed BIST scan signals. tadejm 7880d 03h /ethmac/tags/rel_13/rtl/
226 Igor added WB burst support and repaired BUG when handling TX under-run and retry. tadejm 7880d 04h /ethmac/tags/rel_13/rtl/
221 TxStatus is written after last access to the TX fifo is finished (in case of abort
or retry). TxDone is fixed.		 mohor 7884d 04h /ethmac/tags/rel_13/rtl/
219 txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,
TxDone and TxRetry are generated after the current WISHBONE access is
finished.		 mohor 7887d 04h /ethmac/tags/rel_13/rtl/
218 Typo error fixed. (When using Bist) mohor 7887d 06h /ethmac/tags/rel_13/rtl/
214 Signals for WISHBONE B3 compliant interface added. mohor 7888d 03h /ethmac/tags/rel_13/rtl/
213 Defines changed to have ETH_ prolog.
ETH_WISHBONE_B# define added.		 mohor 7888d 03h /ethmac/tags/rel_13/rtl/

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