URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [tags/] [rel_13/] [rtl/] [verilog/] - Rev 236

Filtering Options

From rev	To rev	Max revs

Search for

Rev	Log message	Author	Age	Path
236	State machine goes from idle to the defer state when CarrierSense is 1. FCS (CRC appending) fixed to check the CrcEn bit also when padding is necessery.	mohor	7872d 15h	/ethmac/tags/rel_13/rtl/verilog/
232	fpga define added.	mohor	7878d 09h	/ethmac/tags/rel_13/rtl/verilog/
229	case changed to casex.	mohor	7884d 07h	/ethmac/tags/rel_13/rtl/verilog/
227	Changed BIST scan signals.	tadejm	7884d 11h	/ethmac/tags/rel_13/rtl/verilog/
226	Igor added WB burst support and repaired BUG when handling TX under-run and retry.	tadejm	7884d 12h	/ethmac/tags/rel_13/rtl/verilog/
221	TxStatus is written after last access to the TX fifo is finished (in case of abort or retry). TxDone is fixed.	mohor	7888d 12h	/ethmac/tags/rel_13/rtl/verilog/
219	txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file, TxDone and TxRetry are generated after the current WISHBONE access is finished.	mohor	7891d 12h	/ethmac/tags/rel_13/rtl/verilog/
218	Typo error fixed. (When using Bist)	mohor	7891d 14h	/ethmac/tags/rel_13/rtl/verilog/
214	Signals for WISHBONE B3 compliant interface added.	mohor	7892d 11h	/ethmac/tags/rel_13/rtl/verilog/
213	Defines changed to have ETH_ prolog. ETH_WISHBONE_B# define added.	mohor	7892d 11h	/ethmac/tags/rel_13/rtl/verilog/
212	Minor $display change.	mohor	7892d 11h	/ethmac/tags/rel_13/rtl/verilog/
211	Bist added.	mohor	7892d 11h	/ethmac/tags/rel_13/rtl/verilog/
210	BIST added.	mohor	7892d 12h	/ethmac/tags/rel_13/rtl/verilog/
204	ETH_VIRTUAL_SILICON_RAM supported (for ASIC implementation).	mohor	7909d 10h	/ethmac/tags/rel_13/rtl/verilog/
203	Virtual Silicon RAM might be used in the ASIC implementation of the ethernet core.	mohor	7909d 10h	/ethmac/tags/rel_13/rtl/verilog/
202	CsMiss added. When address between 0x800 and 0xfff is accessed within Ethernet Core, error acknowledge is generated.	mohor	7912d 11h	/ethmac/tags/rel_13/rtl/verilog/
168	CarrierSenseLost bug fixed when operating in full duplex mode.	mohor	7920d 13h	/ethmac/tags/rel_13/rtl/verilog/
167	Sometimes both RxB_IRQ and RxE_IRQ were activated. Bug fixed.	mohor	7921d 14h	/ethmac/tags/rel_13/rtl/verilog/
166	Reception is possible after RxPointer is read and not after BD is read. For that reason RxBDReady is changed to RxReady. Busy_IRQ interrupt connected. When there is no RxBD ready and frame comes, interrupt is generated.	mohor	7922d 14h	/ethmac/tags/rel_13/rtl/verilog/
165	HASH improvement needed.	mohor	7922d 17h	/ethmac/tags/rel_13/rtl/verilog/

1 2 Next >

Show All

Browse

Tools

Subversion Repositories ethmac

[/] [ethmac/] [tags/] [rel_13/] [rtl/] [verilog/] - Rev 236

Filtering Options