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[/] [ethmac/] [tags/] [rel_13/] [rtl] - Rev 242

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242 Late collision is reported only when not in the full duplex.
Sample is taken (for status) as soon as MRxDV is not valid (regardless
of the received byte cnt).		 tadejm 7846d 07h /ethmac/tags/rel_13/rtl
241 StartIdle state changed (not important the size of the packet).
StartData1 activates only while ByteCnt is smaller than the MaxFrame.		 tadejm 7846d 07h /ethmac/tags/rel_13/rtl
240 All modules are reset with wb_rst instead of the r_Rst. Exception is MII module. tadejm 7846d 07h /ethmac/tags/rel_13/rtl
239 RxError is not generated when small frame reception is enabled and small
frames are received.		 tadejm 7846d 07h /ethmac/tags/rel_13/rtl
238 Defines fixed to use generic RAM by default. mohor 7858d 11h /ethmac/tags/rel_13/rtl
236 State machine goes from idle to the defer state when CarrierSense is 1. FCS (CRC appending) fixed to check the CrcEn bit also when padding is necessery. mohor 7860d 17h /ethmac/tags/rel_13/rtl
232 fpga define added. mohor 7866d 11h /ethmac/tags/rel_13/rtl
229 case changed to casex. mohor 7872d 09h /ethmac/tags/rel_13/rtl
227 Changed BIST scan signals. tadejm 7872d 12h /ethmac/tags/rel_13/rtl
226 Igor added WB burst support and repaired BUG when handling TX under-run and retry. tadejm 7872d 14h /ethmac/tags/rel_13/rtl
221 TxStatus is written after last access to the TX fifo is finished (in case of abort
or retry). TxDone is fixed.		 mohor 7876d 13h /ethmac/tags/rel_13/rtl
219 txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,
TxDone and TxRetry are generated after the current WISHBONE access is
finished.		 mohor 7879d 14h /ethmac/tags/rel_13/rtl
218 Typo error fixed. (When using Bist) mohor 7879d 16h /ethmac/tags/rel_13/rtl
214 Signals for WISHBONE B3 compliant interface added. mohor 7880d 13h /ethmac/tags/rel_13/rtl
213 Defines changed to have ETH_ prolog.
ETH_WISHBONE_B# define added.		 mohor 7880d 13h /ethmac/tags/rel_13/rtl
212 Minor $display change. mohor 7880d 13h /ethmac/tags/rel_13/rtl
211 Bist added. mohor 7880d 13h /ethmac/tags/rel_13/rtl
210 BIST added. mohor 7880d 13h /ethmac/tags/rel_13/rtl
204 ETH_VIRTUAL_SILICON_RAM supported (for ASIC implementation). mohor 7897d 11h /ethmac/tags/rel_13/rtl
203 Virtual Silicon RAM might be used in the ASIC implementation of the ethernet
core.		 mohor 7897d 11h /ethmac/tags/rel_13/rtl
202 CsMiss added. When address between 0x800 and 0xfff is accessed within
Ethernet Core, error acknowledge is generated.		 mohor 7900d 12h /ethmac/tags/rel_13/rtl
168 CarrierSenseLost bug fixed when operating in full duplex mode. mohor 7908d 15h /ethmac/tags/rel_13/rtl
167 Sometimes both RxB_IRQ and RxE_IRQ were activated. Bug fixed. mohor 7909d 15h /ethmac/tags/rel_13/rtl
166 Reception is possible after RxPointer is read and not after BD is read. For
that reason RxBDReady is changed to RxReady.
Busy_IRQ interrupt connected. When there is no RxBD ready and frame
comes, interrupt is generated.		 mohor 7910d 16h /ethmac/tags/rel_13/rtl
165 HASH improvement needed. mohor 7910d 19h /ethmac/tags/rel_13/rtl
164 Ethernet debug registers removed. mohor 7910d 19h /ethmac/tags/rel_13/rtl
161 Error acknowledge is generated when accessing BDs and RST bit in the
MODER register (r_Rst) is set.		 mohor 7911d 16h /ethmac/tags/rel_13/rtl
160 error acknowledge cycle termination added to display. mohor 7911d 17h /ethmac/tags/rel_13/rtl
159 Async reset for WB_ACK_O removed (when core was in reset, it was
impossible to access BDs).
RxPointers and TxPointers names changed to be more descriptive.
TxUnderRun synchronized.		 mohor 7912d 13h /ethmac/tags/rel_13/rtl
150 Debug registers reg1, 2, 3, 4 connected. Synchronization of many signals
changed (bugs fixed). Access to un-alligned buffers fixed. RxAbort signal
was not used OK.		 mohor 7916d 11h /ethmac/tags/rel_13/rtl

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