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[/] [ethmac/] [tags/] [rel_14/] - Rev 236

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236 State machine goes from idle to the defer state when CarrierSense is 1. FCS (CRC appending) fixed to check the CrcEn bit also when padding is necessery. mohor 7866d 01h /ethmac/tags/rel_14
235 rev 4. mohor 7866d 16h /ethmac/tags/rel_14
234 Figure list assed to the revision 3. mohor 7867d 00h /ethmac/tags/rel_14
233 Revision 0.3 released. Some figures added. mohor 7867d 01h /ethmac/tags/rel_14
232 fpga define added. mohor 7871d 20h /ethmac/tags/rel_14
231 Description of Core Modules added (figure). mohor 7873d 21h /ethmac/tags/rel_14
229 case changed to casex. mohor 7877d 18h /ethmac/tags/rel_14
227 Changed BIST scan signals. tadejm 7877d 21h /ethmac/tags/rel_14
226 Igor added WB burst support and repaired BUG when handling TX under-run and retry. tadejm 7877d 23h /ethmac/tags/rel_14
225 Some minor changes. tadejm 7877d 23h /ethmac/tags/rel_14
224 Signals for a wave window in Modelsim. tadejm 7878d 00h /ethmac/tags/rel_14
223 Some code changed due to bug fixes. tadejm 7878d 00h /ethmac/tags/rel_14
221 TxStatus is written after last access to the TX fifo is finished (in case of abort
or retry). TxDone is fixed.		 mohor 7881d 22h /ethmac/tags/rel_14
219 txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,
TxDone and TxRetry are generated after the current WISHBONE access is
finished.		 mohor 7884d 23h /ethmac/tags/rel_14
218 Typo error fixed. (When using Bist) mohor 7885d 01h /ethmac/tags/rel_14
217 Bist supported. mohor 7885d 01h /ethmac/tags/rel_14
216 Bist signals added. mohor 7885d 01h /ethmac/tags/rel_14
215 Bist supported. mohor 7885d 02h /ethmac/tags/rel_14
214 Signals for WISHBONE B3 compliant interface added. mohor 7885d 22h /ethmac/tags/rel_14
213 Defines changed to have ETH_ prolog.
ETH_WISHBONE_B# define added.		 mohor 7885d 22h /ethmac/tags/rel_14
212 Minor $display change. mohor 7885d 22h /ethmac/tags/rel_14
211 Bist added. mohor 7885d 22h /ethmac/tags/rel_14
210 BIST added. mohor 7885d 22h /ethmac/tags/rel_14
209 Just back-up; not completed testbench and some testcases are not
wotking properly yet.		 tadejm 7887d 01h /ethmac/tags/rel_14
208 Virtual Silicon RAMs moved to lib directory tadej 7902d 19h /ethmac/tags/rel_14
207 Virtual Silicon RAM support fixed tadej 7902d 19h /ethmac/tags/rel_14
206 Virtual Silicon RAM added to the simulation. mohor 7902d 19h /ethmac/tags/rel_14
205 ETH_VIRTUAL_SILICON_RAM supported. mohor 7902d 20h /ethmac/tags/rel_14
204 ETH_VIRTUAL_SILICON_RAM supported (for ASIC implementation). mohor 7902d 20h /ethmac/tags/rel_14
203 Virtual Silicon RAM might be used in the ASIC implementation of the ethernet
core.		 mohor 7902d 20h /ethmac/tags/rel_14

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