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Rev Log message Author Age Path
245 Rev 1.7. mohor 7842d 06h /ethmac/tags/rel_14
244 r_Rst signal does not reset any module any more and is removed from the design. mohor 7842d 08h /ethmac/tags/rel_14
243 Late collision is not reported any more. tadejm 7842d 14h /ethmac/tags/rel_14
242 Late collision is reported only when not in the full duplex.
Sample is taken (for status) as soon as MRxDV is not valid (regardless
of the received byte cnt).		 tadejm 7843d 04h /ethmac/tags/rel_14
241 StartIdle state changed (not important the size of the packet).
StartData1 activates only while ByteCnt is smaller than the MaxFrame.		 tadejm 7843d 04h /ethmac/tags/rel_14
240 All modules are reset with wb_rst instead of the r_Rst. Exception is MII module. tadejm 7843d 04h /ethmac/tags/rel_14
239 RxError is not generated when small frame reception is enabled and small
frames are received.		 tadejm 7843d 04h /ethmac/tags/rel_14
238 Defines fixed to use generic RAM by default. mohor 7855d 08h /ethmac/tags/rel_14
236 State machine goes from idle to the defer state when CarrierSense is 1. FCS (CRC appending) fixed to check the CrcEn bit also when padding is necessery. mohor 7857d 14h /ethmac/tags/rel_14
235 rev 4. mohor 7858d 04h /ethmac/tags/rel_14
234 Figure list assed to the revision 3. mohor 7858d 13h /ethmac/tags/rel_14
233 Revision 0.3 released. Some figures added. mohor 7858d 13h /ethmac/tags/rel_14
232 fpga define added. mohor 7863d 08h /ethmac/tags/rel_14
231 Description of Core Modules added (figure). mohor 7865d 09h /ethmac/tags/rel_14
229 case changed to casex. mohor 7869d 06h /ethmac/tags/rel_14
227 Changed BIST scan signals. tadejm 7869d 10h /ethmac/tags/rel_14
226 Igor added WB burst support and repaired BUG when handling TX under-run and retry. tadejm 7869d 11h /ethmac/tags/rel_14
225 Some minor changes. tadejm 7869d 11h /ethmac/tags/rel_14
224 Signals for a wave window in Modelsim. tadejm 7869d 13h /ethmac/tags/rel_14
223 Some code changed due to bug fixes. tadejm 7869d 13h /ethmac/tags/rel_14

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