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252 Just some updates. tadejm 6472d 00h /ethmac/tags/rel_14/
251 When control frame (PAUSE) was sent, status was written in the
eth_wishbone module and both TXB and TXC interrupts were set. Fixed.
Only TXC interrupt is set.
mohor 6472d 00h /ethmac/tags/rel_14/
250 AddressMiss status is connecting to the Rx BD. AddressMiss is identifying
that a frame was received because of the promiscous mode.
mohor 6472d 00h /ethmac/tags/rel_14/
248 wb_rst_i is used for MIIM reset. mohor 6473d 00h /ethmac/tags/rel_14/
246 Since r_Rst bit is not used any more, default value is changed to 0xa000. mohor 6476d 03h /ethmac/tags/rel_14/
245 Rev 1.7. mohor 6476d 21h /ethmac/tags/rel_14/
244 r_Rst signal does not reset any module any more and is removed from the design. mohor 6476d 23h /ethmac/tags/rel_14/
243 Late collision is not reported any more. tadejm 6477d 04h /ethmac/tags/rel_14/
242 Late collision is reported only when not in the full duplex.
Sample is taken (for status) as soon as MRxDV is not valid (regardless
of the received byte cnt).
tadejm 6477d 19h /ethmac/tags/rel_14/
241 StartIdle state changed (not important the size of the packet).
StartData1 activates only while ByteCnt is smaller than the MaxFrame.
tadejm 6477d 19h /ethmac/tags/rel_14/
240 All modules are reset with wb_rst instead of the r_Rst. Exception is MII module. tadejm 6477d 19h /ethmac/tags/rel_14/
239 RxError is not generated when small frame reception is enabled and small
frames are received.
tadejm 6477d 19h /ethmac/tags/rel_14/
238 Defines fixed to use generic RAM by default. mohor 6489d 23h /ethmac/tags/rel_14/
236 State machine goes from idle to the defer state when CarrierSense is 1. FCS (CRC appending) fixed to check the CrcEn bit also when padding is necessery. mohor 6492d 05h /ethmac/tags/rel_14/
235 rev 4. mohor 6492d 19h /ethmac/tags/rel_14/
234 Figure list assed to the revision 3. mohor 6493d 03h /ethmac/tags/rel_14/
233 Revision 0.3 released. Some figures added. mohor 6493d 04h /ethmac/tags/rel_14/
232 fpga define added. mohor 6497d 23h /ethmac/tags/rel_14/
231 Description of Core Modules added (figure). mohor 6500d 00h /ethmac/tags/rel_14/
229 case changed to casex. mohor 6503d 21h /ethmac/tags/rel_14/
227 Changed BIST scan signals. tadejm 6504d 00h /ethmac/tags/rel_14/
226 Igor added WB burst support and repaired BUG when handling TX under-run and retry. tadejm 6504d 02h /ethmac/tags/rel_14/
225 Some minor changes. tadejm 6504d 02h /ethmac/tags/rel_14/
224 Signals for a wave window in Modelsim. tadejm 6504d 03h /ethmac/tags/rel_14/
223 Some code changed due to bug fixes. tadejm 6504d 03h /ethmac/tags/rel_14/
221 TxStatus is written after last access to the TX fifo is finished (in case of abort
or retry). TxDone is fixed.
mohor 6508d 01h /ethmac/tags/rel_14/
219 txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,
TxDone and TxRetry are generated after the current WISHBONE access is
finished.
mohor 6511d 02h /ethmac/tags/rel_14/
218 Typo error fixed. (When using Bist) mohor 6511d 04h /ethmac/tags/rel_14/
217 Bist supported. mohor 6511d 04h /ethmac/tags/rel_14/
216 Bist signals added. mohor 6511d 04h /ethmac/tags/rel_14/

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