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[/] [ethmac/] [tags/] [rel_14/] [bench/] [verilog/] - Rev 338

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Rev Log message Author Age Path
338 root 5478d 14h /ethmac/tags/rel_14/bench/verilog
335 New directory structure. root 5535d 19h /ethmac/tags/rel_14/bench/verilog
271 This commit was manufactured by cvs2svn to create tag 'rel_14'. 7774d 17h /ethmac/tags/rel_14/bench/verilog
267 Full duplex control frames tested. mohor 7829d 13h /ethmac/tags/rel_14/bench/verilog
266 Flow control test almost finished. mohor 7834d 12h /ethmac/tags/rel_14/bench/verilog
263 test_mac_full_duplex_flow_control tests pretty much finished.
TEST 0: INSERT CONTROL FRM. WHILE TRANSMITTING NORMAL
FRM. AT 4 TX BD ( 10Mbps ) finished.
TEST 2: RECEIVE CONTROL FRAMES WITH PASSALL OPTION
TURNED OFF AT ONE RX BD ( 10Mbps ) finished.
mohor 7835d 03h /ethmac/tags/rel_14/bench/verilog
260 test_mac_full_duplex_flow test 0 finished. Sending the control (PAUSE) frame
finished.
mohor 7835d 15h /ethmac/tags/rel_14/bench/verilog
254 Temp version. mohor 7837d 09h /ethmac/tags/rel_14/bench/verilog
252 Just some updates. tadejm 7837d 12h /ethmac/tags/rel_14/bench/verilog
243 Late collision is not reported any more. tadejm 7842d 16h /ethmac/tags/rel_14/bench/verilog
227 Changed BIST scan signals. tadejm 7869d 12h /ethmac/tags/rel_14/bench/verilog
223 Some code changed due to bug fixes. tadejm 7869d 15h /ethmac/tags/rel_14/bench/verilog
216 Bist signals added. mohor 7876d 16h /ethmac/tags/rel_14/bench/verilog
209 Just back-up; not completed testbench and some testcases are not
wotking properly yet.
tadejm 7878d 16h /ethmac/tags/rel_14/bench/verilog
194 Full duplex tests modified and testbench bug repaired. tadej 7897d 15h /ethmac/tags/rel_14/bench/verilog
192 Some additional reports added tadej 7899d 11h /ethmac/tags/rel_14/bench/verilog
191 Bug repaired in eth_phy device tadej 7899d 11h /ethmac/tags/rel_14/bench/verilog
189 Simple testbench that includes eth_cop, eth_host and eth_memory modules.
This testbench is used for testing the whole environment. Use tb_ethernet
testbench for testing just the ethernet MAC core (many tests).
mohor 7899d 13h /ethmac/tags/rel_14/bench/verilog
188 PHY changed. tadej 7900d 09h /ethmac/tags/rel_14/bench/verilog
182 Full duplex test improved. tadej 7901d 11h /ethmac/tags/rel_14/bench/verilog

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