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[/] [ethmac/] [tags/] [rel_14/] [bench/] [verilog/] - Rev 345

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Rev Log message Author Age Path
338 root 5504d 16h /ethmac/tags/rel_14/bench/verilog/
335 New directory structure. root 5561d 22h /ethmac/tags/rel_14/bench/verilog/
271 This commit was manufactured by cvs2svn to create tag 'rel_14'. 7800d 19h /ethmac/tags/rel_14/bench/verilog/
267 Full duplex control frames tested. mohor 7855d 15h /ethmac/tags/rel_14/bench/verilog/
266 Flow control test almost finished. mohor 7860d 14h /ethmac/tags/rel_14/bench/verilog/
263 test_mac_full_duplex_flow_control tests pretty much finished.
TEST 0: INSERT CONTROL FRM. WHILE TRANSMITTING NORMAL
FRM. AT 4 TX BD ( 10Mbps ) finished.
TEST 2: RECEIVE CONTROL FRAMES WITH PASSALL OPTION
TURNED OFF AT ONE RX BD ( 10Mbps ) finished.		 mohor 7861d 05h /ethmac/tags/rel_14/bench/verilog/
260 test_mac_full_duplex_flow test 0 finished. Sending the control (PAUSE) frame
finished.		 mohor 7861d 18h /ethmac/tags/rel_14/bench/verilog/
254 Temp version. mohor 7863d 11h /ethmac/tags/rel_14/bench/verilog/
252 Just some updates. tadejm 7863d 14h /ethmac/tags/rel_14/bench/verilog/
243 Late collision is not reported any more. tadejm 7868d 18h /ethmac/tags/rel_14/bench/verilog/
227 Changed BIST scan signals. tadejm 7895d 15h /ethmac/tags/rel_14/bench/verilog/
223 Some code changed due to bug fixes. tadejm 7895d 18h /ethmac/tags/rel_14/bench/verilog/
216 Bist signals added. mohor 7902d 18h /ethmac/tags/rel_14/bench/verilog/
209 Just back-up; not completed testbench and some testcases are not
wotking properly yet.		 tadejm 7904d 18h /ethmac/tags/rel_14/bench/verilog/
194 Full duplex tests modified and testbench bug repaired. tadej 7923d 17h /ethmac/tags/rel_14/bench/verilog/
192 Some additional reports added tadej 7925d 14h /ethmac/tags/rel_14/bench/verilog/
191 Bug repaired in eth_phy device tadej 7925d 14h /ethmac/tags/rel_14/bench/verilog/
189 Simple testbench that includes eth_cop, eth_host and eth_memory modules.
This testbench is used for testing the whole environment. Use tb_ethernet
testbench for testing just the ethernet MAC core (many tests).		 mohor 7925d 15h /ethmac/tags/rel_14/bench/verilog/
188 PHY changed. tadej 7926d 12h /ethmac/tags/rel_14/bench/verilog/
182 Full duplex test improved. tadej 7927d 14h /ethmac/tags/rel_14/bench/verilog/
181 MIIM test look better. mohor 7927d 16h /ethmac/tags/rel_14/bench/verilog/
180 Bench outputs data to display every 128 bytes. mohor 7930d 12h /ethmac/tags/rel_14/bench/verilog/
179 Beautiful tests merget together mohor 7930d 13h /ethmac/tags/rel_14/bench/verilog/
178 Rearanged testcases mohor 7930d 13h /ethmac/tags/rel_14/bench/verilog/
177 Bug in MIIM fixed. mohor 7930d 17h /ethmac/tags/rel_14/bench/verilog/
170 Headers changed. mohor 7930d 19h /ethmac/tags/rel_14/bench/verilog/
169 New testbench. Thanks to Tadej M - "The Spammer". mohor 7930d 20h /ethmac/tags/rel_14/bench/verilog/
158 Typo fixed. mohor 7935d 15h /ethmac/tags/rel_14/bench/verilog/
157 This testbench will soon be obsolete. Please use tb_ethernet.v mohor 7937d 21h /ethmac/tags/rel_14/bench/verilog/
156 Valid testbench. mohor 7937d 21h /ethmac/tags/rel_14/bench/verilog/

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