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[/] [ethmac/] [tags/] [rel_14/] [bench/] [verilog/] [tb_ethernet.v] - Rev 338

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338 root 5477d 08h /ethmac/tags/rel_14/bench/verilog/tb_ethernet.v
335 New directory structure. root 5534d 13h /ethmac/tags/rel_14/bench/verilog/tb_ethernet.v
271 This commit was manufactured by cvs2svn to create tag 'rel_14'. 7773d 11h /ethmac/tags/rel_14/bench/verilog/tb_ethernet.v
267 Full duplex control frames tested. mohor 7828d 06h /ethmac/tags/rel_14/bench/verilog/tb_ethernet.v
266 Flow control test almost finished. mohor 7833d 05h /ethmac/tags/rel_14/bench/verilog/tb_ethernet.v
263 test_mac_full_duplex_flow_control tests pretty much finished.
TEST 0: INSERT CONTROL FRM. WHILE TRANSMITTING NORMAL
FRM. AT 4 TX BD ( 10Mbps ) finished.
TEST 2: RECEIVE CONTROL FRAMES WITH PASSALL OPTION
TURNED OFF AT ONE RX BD ( 10Mbps ) finished.		 mohor 7833d 21h /ethmac/tags/rel_14/bench/verilog/tb_ethernet.v
260 test_mac_full_duplex_flow test 0 finished. Sending the control (PAUSE) frame
finished.		 mohor 7834d 09h /ethmac/tags/rel_14/bench/verilog/tb_ethernet.v
254 Temp version. mohor 7836d 02h /ethmac/tags/rel_14/bench/verilog/tb_ethernet.v
252 Just some updates. tadejm 7836d 05h /ethmac/tags/rel_14/bench/verilog/tb_ethernet.v
243 Late collision is not reported any more. tadejm 7841d 10h /ethmac/tags/rel_14/bench/verilog/tb_ethernet.v
227 Changed BIST scan signals. tadejm 7868d 06h /ethmac/tags/rel_14/bench/verilog/tb_ethernet.v
223 Some code changed due to bug fixes. tadejm 7868d 09h /ethmac/tags/rel_14/bench/verilog/tb_ethernet.v
209 Just back-up; not completed testbench and some testcases are not
wotking properly yet.		 tadejm 7877d 10h /ethmac/tags/rel_14/bench/verilog/tb_ethernet.v
194 Full duplex tests modified and testbench bug repaired. tadej 7896d 08h /ethmac/tags/rel_14/bench/verilog/tb_ethernet.v
192 Some additional reports added tadej 7898d 05h /ethmac/tags/rel_14/bench/verilog/tb_ethernet.v
182 Full duplex test improved. tadej 7900d 05h /ethmac/tags/rel_14/bench/verilog/tb_ethernet.v
181 MIIM test look better. mohor 7900d 08h /ethmac/tags/rel_14/bench/verilog/tb_ethernet.v
180 Bench outputs data to display every 128 bytes. mohor 7903d 04h /ethmac/tags/rel_14/bench/verilog/tb_ethernet.v
179 Beautiful tests merget together mohor 7903d 04h /ethmac/tags/rel_14/bench/verilog/tb_ethernet.v
178 Rearanged testcases mohor 7903d 04h /ethmac/tags/rel_14/bench/verilog/tb_ethernet.v

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