URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [tags/] [rel_14/] [rtl/] [verilog/] - Rev 165

Rev	Log message	Author	Age	Path
132	LinkFailRegister is reflecting the status of the PHY's link fail status bit.	mohor	7934d 13h	/ethmac/tags/rel_14/rtl/verilog/
131	LinkFail signal was not latching appropriate bit.	mohor	7934d 13h	/ethmac/tags/rel_14/rtl/verilog/
129	Traffic cop with 2 wishbone master interfaces and 2 wishbona slave interfaces: - Host connects to the master interface - Ethernet master (DMA) connects to the second master interface - Memory interface connects to the slave interface - Ethernet slave interface (access to registers and BDs) connects to second slave interface	mohor	7934d 14h	/ethmac/tags/rel_14/rtl/verilog/
127	WriteRxDataToMemory signal changed so end of frame (when last word is written to fifo) is changed.	mohor	7954d 13h	/ethmac/tags/rel_14/rtl/verilog/
126	InvalidSymbol generation changed.	mohor	7954d 13h	/ethmac/tags/rel_14/rtl/verilog/
125	RxAbort changed. Packets received with MRxErr (from PHY) are also aborted.	mohor	7954d 13h	/ethmac/tags/rel_14/rtl/verilog/
122	ethernet spram added. So far a generic ram and xilinx RAMB4 are used.	mohor	7956d 15h	/ethmac/tags/rel_14/rtl/verilog/
120	Unused files removed.	mohor	7956d 16h	/ethmac/tags/rel_14/rtl/verilog/
119	Ram , used for BDs changed from generic_spram to eth_spram_256x32.	mohor	7956d 16h	/ethmac/tags/rel_14/rtl/verilog/
118	ShiftEnded synchronization changed.	mohor	7960d 07h	/ethmac/tags/rel_14/rtl/verilog/