URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [tags/] [rel_14/] [rtl/] [verilog/] - Rev 61

Rev	Log message	Author	Age	Path
37	Link in the header changed.	mohor	8135d 03h	/ethmac/tags/rel_14/rtl/verilog/
34	RX_BD_NUM changed to TX_BD_NUM (holds number of TX descriptors instead of the number of RX descriptors).	mohor	8183d 23h	/ethmac/tags/rel_14/rtl/verilog/
33	ETH_RX_BD_ADR register deleted. ETH_RX_BD_NUM is used instead.	mohor	8184d 03h	/ethmac/tags/rel_14/rtl/verilog/
32	ETH_RX_BD_ADR register deleted. ETH_RX_BD_NUM is used instead.	mohor	8184d 04h	/ethmac/tags/rel_14/rtl/verilog/
29	Generic memory model is used. Defines are changed for the same reason.	mohor	8206d 00h	/ethmac/tags/rel_14/rtl/verilog/
24	Log file added.	mohor	8231d 02h	/ethmac/tags/rel_14/rtl/verilog/
23	Number of addresses (wb_adr_i) minimized.	mohor	8231d 03h	/ethmac/tags/rel_14/rtl/verilog/
22	eth_timescale.v changed to timescale.v This is done because of the simulation of the few cores in a one joined project.	mohor	8231d 05h	/ethmac/tags/rel_14/rtl/verilog/
21	Status signals changed, Adress decoding changed, interrupt controller added.	mohor	8232d 02h	/ethmac/tags/rel_14/rtl/verilog/
20	Defines changed (All precede with ETH_). Small changes because some tools generate warnings when two operands are together. Synchronization between two clocks domains in eth_wishbonedma.v is changed (due to ASIC demands).	mohor	8255d 23h	/ethmac/tags/rel_14/rtl/verilog/