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[/] [ethmac/] [tags/] [rel_14/] [rtl/] [verilog/] - Rev 72


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Rev Log message Author Age Path
72 Retry is not activated when a Tx Underrun occured mohor 6860d 11h /ethmac/tags/rel_14/rtl/verilog/
70 Small fixes. mohor 6864d 14h /ethmac/tags/rel_14/rtl/verilog/
69 Define missmatch fixed. mohor 6865d 11h /ethmac/tags/rel_14/rtl/verilog/
68 Registered trimmed. Unused registers removed. mohor 6866d 10h /ethmac/tags/rel_14/rtl/verilog/
67 EXTERNAL_DMA used instead of WISHBONE_DMA. mohor 6866d 11h /ethmac/tags/rel_14/rtl/verilog/
65 Testbench fixed, code simplified, unused signals removed. mohor 6866d 17h /ethmac/tags/rel_14/rtl/verilog/
64 Status was not written correctly when frames were discarted because of
address mismatch.
mohor 6867d 07h /ethmac/tags/rel_14/rtl/verilog/
63 RxAbort is connected differently. mohor 6867d 10h /ethmac/tags/rel_14/rtl/verilog/
62 RxAbort is an output. No need to have is declared as wire. mohor 6867d 10h /ethmac/tags/rel_14/rtl/verilog/
61 RxStartFrm cleared when abort or retry comes. mohor 6867d 12h /ethmac/tags/rel_14/rtl/verilog/
60 Changes that were lost when updating from 1.5 to 1.8 fixed. mohor 6867d 12h /ethmac/tags/rel_14/rtl/verilog/
59 Changes that were lost when updating from 1.11 to 1.14 fixed. mohor 6867d 13h /ethmac/tags/rel_14/rtl/verilog/
58 File format changed. mohor 6867d 13h /ethmac/tags/rel_14/rtl/verilog/
57 Format of the file changed a bit. mohor 6867d 13h /ethmac/tags/rel_14/rtl/verilog/
56 File format fixed a bit. mohor 6867d 13h /ethmac/tags/rel_14/rtl/verilog/
55 Changed that were lost with last update put back to the file. mohor 6867d 13h /ethmac/tags/rel_14/rtl/verilog/
54 Addition of new module eth_addrcheck.v billditt 6868d 03h /ethmac/tags/rel_14/rtl/verilog/
53 Addition of new module eth_addrcheck.v billditt 6868d 03h /ethmac/tags/rel_14/rtl/verilog/
52 Modified for Address Checking,
addition of eth_addrcheck.v
billditt 6868d 04h /ethmac/tags/rel_14/rtl/verilog/
50 checks destination address for Unicast, Multicast and Broadcast ops billditt 6868d 05h /ethmac/tags/rel_14/rtl/verilog/

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