URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [tags/] [rel_14/] [rtl/] [verilog/] [eth_defines.v] - Rev 213

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

From rev	To rev	Max revs

Search for

Rev	Log message	Author	Age	Path
213	Defines changed to have ETH_ prolog. ETH_WISHBONE_B# define added.	mohor	7873d 17h	/ethmac/tags/rel_14/rtl/verilog/eth_defines.v
211	Bist added.	mohor	7873d 17h	/ethmac/tags/rel_14/rtl/verilog/eth_defines.v
203	Virtual Silicon RAM might be used in the ASIC implementation of the ethernet core.	mohor	7890d 15h	/ethmac/tags/rel_14/rtl/verilog/eth_defines.v
145	Defines for control registers added (ETH_TXCTRL and ETH_RXCTRL).	mohor	7909d 15h	/ethmac/tags/rel_14/rtl/verilog/eth_defines.v
137	Defines for register width added. mii_rst signal in MIIMODER register changed.	mohor	7928d 11h	/ethmac/tags/rel_14/rtl/verilog/eth_defines.v
134	Register TX_BD_NUM is changed so it contains value of the Tx buffer descriptors. No need to multiply or devide any more.	mohor	7930d 14h	/ethmac/tags/rel_14/rtl/verilog/eth_defines.v
119	Ram , used for BDs changed from generic_spram to eth_spram_256x32.	mohor	7952d 18h	/ethmac/tags/rel_14/rtl/verilog/eth_defines.v
106	Outputs registered. Reset changed for eth_wishbone module.	mohor	8033d 23h	/ethmac/tags/rel_14/rtl/verilog/eth_defines.v
105	Compiler directives added. Tx and Rx fifo size incremented. A "late collision" bug fixed.	mohor	8043d 01h	/ethmac/tags/rel_14/rtl/verilog/eth_defines.v
92	Some defines that are used in testbench only were moved to tb_eth_defines.v file.	mohor	8078d 21h	/ethmac/tags/rel_14/rtl/verilog/eth_defines.v
73	Number of interrupts changed	mohor	8099d 17h	/ethmac/tags/rel_14/rtl/verilog/eth_defines.v
68	Registered trimmed. Unused registers removed.	mohor	8109d 20h	/ethmac/tags/rel_14/rtl/verilog/eth_defines.v
67	EXTERNAL_DMA used instead of WISHBONE_DMA.	mohor	8109d 20h	/ethmac/tags/rel_14/rtl/verilog/eth_defines.v
55	Changed that were lost with last update put back to the file.	mohor	8110d 23h	/ethmac/tags/rel_14/rtl/verilog/eth_defines.v
52	Modified for Address Checking, addition of eth_addrcheck.v	billditt	8111d 13h	/ethmac/tags/rel_14/rtl/verilog/eth_defines.v
46	HASH0 and HASH1 registers added.	mohor	8113d 17h	/ethmac/tags/rel_14/rtl/verilog/eth_defines.v
42	Rx status is written back to the BD.	mohor	8117d 17h	/ethmac/tags/rel_14/rtl/verilog/eth_defines.v
40	Both rx and tx part are finished. Tested with wb_clk_i between 10 and 200 MHz. Statuses, overrun, control frame transmission and reception still need to be fixed.	mohor	8120d 17h	/ethmac/tags/rel_14/rtl/verilog/eth_defines.v
37	Link in the header changed.	mohor	8133d 23h	/ethmac/tags/rel_14/rtl/verilog/eth_defines.v
34	RX_BD_NUM changed to TX_BD_NUM (holds number of TX descriptors instead of the number of RX descriptors).	mohor	8182d 19h	/ethmac/tags/rel_14/rtl/verilog/eth_defines.v

1 2 Next >

Show All

Browse

Tools

Subversion Repositories ethmac

[/] [ethmac/] [tags/] [rel_14/] [rtl/] [verilog/] [eth_defines.v] - Rev 213

Filtering Options