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[/] [ethmac/] [tags/] [rel_14/] [rtl/] [verilog/] [eth_top.v] - Rev 164

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Rev Log message Author Age Path
164 Ethernet debug registers removed. mohor 7901d 01h /ethmac/tags/rel_14/rtl/verilog/eth_top.v
161 Error acknowledge is generated when accessing BDs and RST bit in the
MODER register (r_Rst) is set.		 mohor 7901d 23h /ethmac/tags/rel_14/rtl/verilog/eth_top.v
149 Signals related to the control frames connected. Debug registers reg1, 2, 3, 4
connected.		 mohor 7906d 17h /ethmac/tags/rel_14/rtl/verilog/eth_top.v
125 RxAbort changed. Packets received with MRxErr (from PHY) are also
aborted.		 mohor 7947d 18h /ethmac/tags/rel_14/rtl/verilog/eth_top.v
114 EXTERNAL_DMA removed. External DMA not supported. mohor 7955d 17h /ethmac/tags/rel_14/rtl/verilog/eth_top.v
106 Outputs registered. Reset changed for eth_wishbone module. mohor 8031d 02h /ethmac/tags/rel_14/rtl/verilog/eth_top.v
103 Wishbone signals are registered when ETH_REGISTERED_OUTPUTS is
selected in eth_defines.v		 mohor 8041d 22h /ethmac/tags/rel_14/rtl/verilog/eth_top.v
95 md_padoen_o changed to md_padoe_o. Signal was always active high, just
name was incorrect.		 mohor 8069d 22h /ethmac/tags/rel_14/rtl/verilog/eth_top.v
80 Small fixes for external/internal DMA missmatches. mohor 8096d 19h /ethmac/tags/rel_14/rtl/verilog/eth_top.v
76 Interrupts changed in the top file mohor 8096d 20h /ethmac/tags/rel_14/rtl/verilog/eth_top.v
70 Small fixes. mohor 8105d 01h /ethmac/tags/rel_14/rtl/verilog/eth_top.v
68 Registered trimmed. Unused registers removed. mohor 8106d 22h /ethmac/tags/rel_14/rtl/verilog/eth_top.v
67 EXTERNAL_DMA used instead of WISHBONE_DMA. mohor 8106d 23h /ethmac/tags/rel_14/rtl/verilog/eth_top.v
65 Testbench fixed, code simplified, unused signals removed. mohor 8107d 05h /ethmac/tags/rel_14/rtl/verilog/eth_top.v
63 RxAbort is connected differently. mohor 8107d 22h /ethmac/tags/rel_14/rtl/verilog/eth_top.v
59 Changes that were lost when updating from 1.11 to 1.14 fixed. mohor 8108d 00h /ethmac/tags/rel_14/rtl/verilog/eth_top.v
52 Modified for Address Checking,
addition of eth_addrcheck.v		 billditt 8108d 16h /ethmac/tags/rel_14/rtl/verilog/eth_top.v
47 HASH0 and HASH1 registers added. Registers address width was
changed to 8 bits.		 mohor 8110d 19h /ethmac/tags/rel_14/rtl/verilog/eth_top.v
43 Tx status is written back to the BD. mohor 8112d 03h /ethmac/tags/rel_14/rtl/verilog/eth_top.v
42 Rx status is written back to the BD. mohor 8114d 19h /ethmac/tags/rel_14/rtl/verilog/eth_top.v

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