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[/] [ethmac/] [tags/] [rel_14/] [rtl/] [verilog/] [eth_transmitcontrol.v] - Rev 257

Rev	Log message	Author	Age	Path
257	When TxUsedData and CtrlMux occur at the same time, byte counter needs to be incremented by 2. Signal IncrementByteCntBy2 added for that reason.	mohor	7832d 22h	/ethmac/tags/rel_14/rtl/verilog/eth_transmitcontrol.v
251	When control frame (PAUSE) was sent, status was written in the eth_wishbone module and both TXB and TXC interrupts were set. Fixed. Only TXC interrupt is set.	mohor	7834d 05h	/ethmac/tags/rel_14/rtl/verilog/eth_transmitcontrol.v
37	Link in the header changed.	mohor	8134d 12h	/ethmac/tags/rel_14/rtl/verilog/eth_transmitcontrol.v
22	eth_timescale.v changed to timescale.v This is done because of the simulation of the few cores in a one joined project.	mohor	8230d 14h	/ethmac/tags/rel_14/rtl/verilog/eth_transmitcontrol.v
18	Few little NCSIM warnings fixed.	mohor	8268d 08h	/ethmac/tags/rel_14/rtl/verilog/eth_transmitcontrol.v
15	A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex). Include files fixed to contain no path. File names and module names changed ta have a eth_ prologue in the name. File eth_timescale.v is used to define timescale All pin names on the top module are changed to contain _I, _O or _OE at the end. Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O and Mdo_OE. The bidirectional signal must be created on the top level. This is done due to the ASIC tools.	mohor	8304d 08h	/ethmac/tags/rel_14/rtl/verilog/eth_transmitcontrol.v