URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [tags/] [rel_14/] [rtl/] [verilog/] [eth_wishbone.v] - Rev 210

Rev	Log message	Author	Age	Path
90	casex changed with case, fifo reset changed.	mohor	8084d 03h	/ethmac/tags/rel_14/rtl/verilog/eth_wishbone.v
88	rx_fifo was not always cleared ok. Fixed.	mohor	8094d 00h	/ethmac/tags/rel_14/rtl/verilog/eth_wishbone.v
87	Status was not latched correctly sometimes. Fixed.	mohor	8094d 02h	/ethmac/tags/rel_14/rtl/verilog/eth_wishbone.v
86	Big Endian problem when sending frames fixed.	mohor	8095d 09h	/ethmac/tags/rel_14/rtl/verilog/eth_wishbone.v
82	Byte ordering changed (Big Endian used). casex changed with case because Xilinx Foundation had problems. Tested in HW. It WORKS.	mohor	8100d 21h	/ethmac/tags/rel_14/rtl/verilog/eth_wishbone.v
80	Small fixes for external/internal DMA missmatches.	mohor	8104d 23h	/ethmac/tags/rel_14/rtl/verilog/eth_wishbone.v
77	Interrupts changed	mohor	8105d 00h	/ethmac/tags/rel_14/rtl/verilog/eth_wishbone.v
64	Status was not written correctly when frames were discarted because of address mismatch.	mohor	8115d 23h	/ethmac/tags/rel_14/rtl/verilog/eth_wishbone.v
61	RxStartFrm cleared when abort or retry comes.	mohor	8116d 04h	/ethmac/tags/rel_14/rtl/verilog/eth_wishbone.v
60	Changes that were lost when updating from 1.5 to 1.8 fixed.	mohor	8116d 04h	/ethmac/tags/rel_14/rtl/verilog/eth_wishbone.v