URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

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[/] [ethmac/] [tags/] [rel_14/] [rtl/] [verilog/] [eth_wishbone.v] - Rev 335

Rev	Log message	Author	Age	Path
127	WriteRxDataToMemory signal changed so end of frame (when last word is written to fifo) is changed.	mohor	7956d 05h	/ethmac/tags/rel_14/rtl/verilog/eth_wishbone.v
119	Ram , used for BDs changed from generic_spram to eth_spram_256x32.	mohor	7958d 08h	/ethmac/tags/rel_14/rtl/verilog/eth_wishbone.v
118	ShiftEnded synchronization changed.	mohor	7961d 23h	/ethmac/tags/rel_14/rtl/verilog/eth_wishbone.v
115	RxBDAddress takes `ETH_TX_BD_NUM_DEF value after reset.	mohor	7963d 07h	/ethmac/tags/rel_14/rtl/verilog/eth_wishbone.v
113	RxPointer bug fixed.	mohor	7970d 21h	/ethmac/tags/rel_14/rtl/verilog/eth_wishbone.v
112	Previous bug wasn't succesfully removed. Now fixed.	mohor	7971d 10h	/ethmac/tags/rel_14/rtl/verilog/eth_wishbone.v
111	Master state machine had a bug when switching from master write to master read.	mohor	7972d 00h	/ethmac/tags/rel_14/rtl/verilog/eth_wishbone.v
110	m_wb_cyc_o signal released after every single transfer.	mohor	7972d 03h	/ethmac/tags/rel_14/rtl/verilog/eth_wishbone.v
106	Outputs registered. Reset changed for eth_wishbone module.	mohor	8039d 13h	/ethmac/tags/rel_14/rtl/verilog/eth_wishbone.v
105	Compiler directives added. Tx and Rx fifo size incremented. A "late collision" bug fixed.	mohor	8048d 15h	/ethmac/tags/rel_14/rtl/verilog/eth_wishbone.v