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[/] [ethmac/] [tags/] [rel_14/] [rtl/] [verilog/] [eth_wishbone.v] - Rev 338

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338 root 4160d 03h /ethmac/tags/rel_14/rtl/verilog/eth_wishbone.v
335 New directory structure. root 4217d 08h /ethmac/tags/rel_14/rtl/verilog/eth_wishbone.v
271 This commit was manufactured by cvs2svn to create tag 'rel_14'. 6456d 06h /ethmac/tags/rel_14/rtl/verilog/eth_wishbone.v
270 When receiving normal data frame and RxFlow control was switched on, RXB
interrupt was not set.
mohor 6456d 06h /ethmac/tags/rel_14/rtl/verilog/eth_wishbone.v
269 When in full duplex, transmit was sometimes blocked. Fixed. mohor 6457d 06h /ethmac/tags/rel_14/rtl/verilog/eth_wishbone.v
264 Registers RxStatusWrite_rck and RxStatusWriteLatched were not used
anywhere. Removed.
mohor 6516d 05h /ethmac/tags/rel_14/rtl/verilog/eth_wishbone.v
261 Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
synchronized.
mohor 6516d 17h /ethmac/tags/rel_14/rtl/verilog/eth_wishbone.v
250 AddressMiss status is connecting to the Rx BD. AddressMiss is identifying
that a frame was received because of the promiscous mode.
mohor 6519d 01h /ethmac/tags/rel_14/rtl/verilog/eth_wishbone.v
239 RxError is not generated when small frame reception is enabled and small
frames are received.
tadejm 6524d 20h /ethmac/tags/rel_14/rtl/verilog/eth_wishbone.v
229 case changed to casex. mohor 6550d 22h /ethmac/tags/rel_14/rtl/verilog/eth_wishbone.v
227 Changed BIST scan signals. tadejm 6551d 01h /ethmac/tags/rel_14/rtl/verilog/eth_wishbone.v
226 Igor added WB burst support and repaired BUG when handling TX under-run and retry. tadejm 6551d 03h /ethmac/tags/rel_14/rtl/verilog/eth_wishbone.v
221 TxStatus is written after last access to the TX fifo is finished (in case of abort
or retry). TxDone is fixed.
mohor 6555d 02h /ethmac/tags/rel_14/rtl/verilog/eth_wishbone.v
219 txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,
TxDone and TxRetry are generated after the current WISHBONE access is
finished.
mohor 6558d 03h /ethmac/tags/rel_14/rtl/verilog/eth_wishbone.v
210 BIST added. mohor 6559d 02h /ethmac/tags/rel_14/rtl/verilog/eth_wishbone.v
167 Sometimes both RxB_IRQ and RxE_IRQ were activated. Bug fixed. mohor 6588d 04h /ethmac/tags/rel_14/rtl/verilog/eth_wishbone.v
166 Reception is possible after RxPointer is read and not after BD is read. For
that reason RxBDReady is changed to RxReady.
Busy_IRQ interrupt connected. When there is no RxBD ready and frame
comes, interrupt is generated.
mohor 6589d 05h /ethmac/tags/rel_14/rtl/verilog/eth_wishbone.v
164 Ethernet debug registers removed. mohor 6589d 08h /ethmac/tags/rel_14/rtl/verilog/eth_wishbone.v
159 Async reset for WB_ACK_O removed (when core was in reset, it was
impossible to access BDs).
RxPointers and TxPointers names changed to be more descriptive.
TxUnderRun synchronized.
mohor 6591d 02h /ethmac/tags/rel_14/rtl/verilog/eth_wishbone.v
150 Debug registers reg1, 2, 3, 4 connected. Synchronization of many signals
changed (bugs fixed). Access to un-alligned buffers fixed. RxAbort signal
was not used OK.
mohor 6595d 00h /ethmac/tags/rel_14/rtl/verilog/eth_wishbone.v

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