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Rev Log message Author Age Path
234 Figure list assed to the revision 3. mohor 6498d 15h /ethmac/tags/rel_15/
233 Revision 0.3 released. Some figures added. mohor 6498d 16h /ethmac/tags/rel_15/
232 fpga define added. mohor 6503d 11h /ethmac/tags/rel_15/
231 Description of Core Modules added (figure). mohor 6505d 12h /ethmac/tags/rel_15/
229 case changed to casex. mohor 6509d 09h /ethmac/tags/rel_15/
227 Changed BIST scan signals. tadejm 6509d 12h /ethmac/tags/rel_15/
226 Igor added WB burst support and repaired BUG when handling TX under-run and retry. tadejm 6509d 14h /ethmac/tags/rel_15/
225 Some minor changes. tadejm 6509d 14h /ethmac/tags/rel_15/
224 Signals for a wave window in Modelsim. tadejm 6509d 15h /ethmac/tags/rel_15/
223 Some code changed due to bug fixes. tadejm 6509d 15h /ethmac/tags/rel_15/
221 TxStatus is written after last access to the TX fifo is finished (in case of abort
or retry). TxDone is fixed.
mohor 6513d 13h /ethmac/tags/rel_15/
219 txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,
TxDone and TxRetry are generated after the current WISHBONE access is
finished.
mohor 6516d 14h /ethmac/tags/rel_15/
218 Typo error fixed. (When using Bist) mohor 6516d 16h /ethmac/tags/rel_15/
217 Bist supported. mohor 6516d 16h /ethmac/tags/rel_15/
216 Bist signals added. mohor 6516d 16h /ethmac/tags/rel_15/
215 Bist supported. mohor 6516d 17h /ethmac/tags/rel_15/
214 Signals for WISHBONE B3 compliant interface added. mohor 6517d 13h /ethmac/tags/rel_15/
213 Defines changed to have ETH_ prolog.
ETH_WISHBONE_B# define added.
mohor 6517d 13h /ethmac/tags/rel_15/
212 Minor $display change. mohor 6517d 13h /ethmac/tags/rel_15/
211 Bist added. mohor 6517d 13h /ethmac/tags/rel_15/
210 BIST added. mohor 6517d 13h /ethmac/tags/rel_15/
209 Just back-up; not completed testbench and some testcases are not
wotking properly yet.
tadejm 6518d 16h /ethmac/tags/rel_15/
208 Virtual Silicon RAMs moved to lib directory tadej 6534d 10h /ethmac/tags/rel_15/
207 Virtual Silicon RAM support fixed tadej 6534d 10h /ethmac/tags/rel_15/
206 Virtual Silicon RAM added to the simulation. mohor 6534d 10h /ethmac/tags/rel_15/
205 ETH_VIRTUAL_SILICON_RAM supported. mohor 6534d 11h /ethmac/tags/rel_15/
204 ETH_VIRTUAL_SILICON_RAM supported (for ASIC implementation). mohor 6534d 11h /ethmac/tags/rel_15/
203 Virtual Silicon RAM might be used in the ASIC implementation of the ethernet
core.
mohor 6534d 11h /ethmac/tags/rel_15/
202 CsMiss added. When address between 0x800 and 0xfff is accessed within
Ethernet Core, error acknowledge is generated.
mohor 6537d 12h /ethmac/tags/rel_15/
201 Core size added to the document. mohor 6537d 13h /ethmac/tags/rel_15/

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