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246 Since r_Rst bit is not used any more, default value is changed to 0xa000. mohor 6229d 00h /ethmac/tags/rel_15/
245 Rev 1.7. mohor 6229d 18h /ethmac/tags/rel_15/
244 r_Rst signal does not reset any module any more and is removed from the design. mohor 6229d 20h /ethmac/tags/rel_15/
243 Late collision is not reported any more. tadejm 6230d 02h /ethmac/tags/rel_15/
242 Late collision is reported only when not in the full duplex.
Sample is taken (for status) as soon as MRxDV is not valid (regardless
of the received byte cnt).
tadejm 6230d 16h /ethmac/tags/rel_15/
241 StartIdle state changed (not important the size of the packet).
StartData1 activates only while ByteCnt is smaller than the MaxFrame.
tadejm 6230d 16h /ethmac/tags/rel_15/
240 All modules are reset with wb_rst instead of the r_Rst. Exception is MII module. tadejm 6230d 16h /ethmac/tags/rel_15/
239 RxError is not generated when small frame reception is enabled and small
frames are received.
tadejm 6230d 17h /ethmac/tags/rel_15/
238 Defines fixed to use generic RAM by default. mohor 6242d 21h /ethmac/tags/rel_15/
236 State machine goes from idle to the defer state when CarrierSense is 1. FCS (CRC appending) fixed to check the CrcEn bit also when padding is necessery. mohor 6245d 02h /ethmac/tags/rel_15/
235 rev 4. mohor 6245d 17h /ethmac/tags/rel_15/
234 Figure list assed to the revision 3. mohor 6246d 01h /ethmac/tags/rel_15/
233 Revision 0.3 released. Some figures added. mohor 6246d 01h /ethmac/tags/rel_15/
232 fpga define added. mohor 6250d 20h /ethmac/tags/rel_15/
231 Description of Core Modules added (figure). mohor 6252d 21h /ethmac/tags/rel_15/
229 case changed to casex. mohor 6256d 18h /ethmac/tags/rel_15/
227 Changed BIST scan signals. tadejm 6256d 22h /ethmac/tags/rel_15/
226 Igor added WB burst support and repaired BUG when handling TX under-run and retry. tadejm 6256d 23h /ethmac/tags/rel_15/
225 Some minor changes. tadejm 6256d 23h /ethmac/tags/rel_15/
224 Signals for a wave window in Modelsim. tadejm 6257d 01h /ethmac/tags/rel_15/

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