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[/] [ethmac/] [tags/] [rel_15/] [bench/] - Rev 155

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Rev Log message Author Age Path
155 Minor changes. mohor 6626d 09h /ethmac/tags/rel_15/bench/
124 Define ETH_MIIMODER_RST corrected to 0x00000400. mohor 6669d 03h /ethmac/tags/rel_15/bench/
121 gsr added for use when ETH_XILINX_RAMB4 define is set. mohor 6671d 04h /ethmac/tags/rel_15/bench/
117 Clock mrx_clk set to 2.5 MHz. mohor 6675d 06h /ethmac/tags/rel_15/bench/
116 Testing environment also includes traffic cop, memory interface and host
interface.
mohor 6675d 06h /ethmac/tags/rel_15/bench/
108 Testbench supports unaligned accesses. mohor 6752d 10h /ethmac/tags/rel_15/bench/
107 TX_BUF_BASE changed. mohor 6752d 10h /ethmac/tags/rel_15/bench/
92 Some defines that are used in testbench only were moved to tb_eth_defines.v
file.
mohor 6797d 07h /ethmac/tags/rel_15/bench/
80 Small fixes for external/internal DMA missmatches. mohor 6818d 03h /ethmac/tags/rel_15/bench/
67 EXTERNAL_DMA used instead of WISHBONE_DMA. mohor 6828d 07h /ethmac/tags/rel_15/bench/
66 Testbench fixed, code simplified, unused signals removed. mohor 6828d 13h /ethmac/tags/rel_15/bench/
51 Added separate tests for Multicast, Unicast, Broadcast billditt 6830d 00h /ethmac/tags/rel_15/bench/
49 HASH0 and HASH1 register read/write added. mohor 6832d 00h /ethmac/tags/rel_15/bench/
41 non-DMA host interface added. Select the right configutation in eth_defines. mohor 6838d 06h /ethmac/tags/rel_15/bench/
36 TX_BD_NUM register added instead of the RB_BD_ADDR. mohor 6898d 08h /ethmac/tags/rel_15/bench/
23 Number of addresses (wb_adr_i) minimized. mohor 6948d 09h /ethmac/tags/rel_15/bench/
22 eth_timescale.v changed to timescale.v This is done because of the
simulation of the few cores in a one joined project.
mohor 6948d 11h /ethmac/tags/rel_15/bench/
19 Defines changed (All precede with ETH_). Small changes because some
tools generate warnings when two operands are together. Synchronization
between two clocks domains in eth_wishbonedma.v is changed (due to ASIC
demands).
mohor 6973d 05h /ethmac/tags/rel_15/bench/
17 Signal names changed on the top level for easier pad insertion (ASIC). mohor 7013d 06h /ethmac/tags/rel_15/bench/
15 A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
Include files fixed to contain no path.
File names and module names changed ta have a eth_ prologue in the name.
File eth_timescale.v is used to define timescale
All pin names on the top module are changed to contain _I, _O or _OE at the end.
Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
and Mdo_OE. The bidirectional signal must be created on the top level. This
is done due to the ASIC tools.
mohor 7022d 05h /ethmac/tags/rel_15/bench/

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