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[/] [ethmac/] [tags/] [rel_15/] [rtl/] - Rev 241

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241 StartIdle state changed (not important the size of the packet).
StartData1 activates only while ByteCnt is smaller than the MaxFrame.
tadejm 6477d 17h /ethmac/tags/rel_15/rtl/
240 All modules are reset with wb_rst instead of the r_Rst. Exception is MII module. tadejm 6477d 17h /ethmac/tags/rel_15/rtl/
239 RxError is not generated when small frame reception is enabled and small
frames are received.
tadejm 6477d 17h /ethmac/tags/rel_15/rtl/
238 Defines fixed to use generic RAM by default. mohor 6489d 21h /ethmac/tags/rel_15/rtl/
236 State machine goes from idle to the defer state when CarrierSense is 1. FCS (CRC appending) fixed to check the CrcEn bit also when padding is necessery. mohor 6492d 03h /ethmac/tags/rel_15/rtl/
232 fpga define added. mohor 6497d 21h /ethmac/tags/rel_15/rtl/
229 case changed to casex. mohor 6503d 19h /ethmac/tags/rel_15/rtl/
227 Changed BIST scan signals. tadejm 6503d 23h /ethmac/tags/rel_15/rtl/
226 Igor added WB burst support and repaired BUG when handling TX under-run and retry. tadejm 6504d 00h /ethmac/tags/rel_15/rtl/
221 TxStatus is written after last access to the TX fifo is finished (in case of abort
or retry). TxDone is fixed.
mohor 6507d 23h /ethmac/tags/rel_15/rtl/
219 txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,
TxDone and TxRetry are generated after the current WISHBONE access is
finished.
mohor 6511d 00h /ethmac/tags/rel_15/rtl/
218 Typo error fixed. (When using Bist) mohor 6511d 02h /ethmac/tags/rel_15/rtl/
214 Signals for WISHBONE B3 compliant interface added. mohor 6511d 23h /ethmac/tags/rel_15/rtl/
213 Defines changed to have ETH_ prolog.
ETH_WISHBONE_B# define added.
mohor 6511d 23h /ethmac/tags/rel_15/rtl/
212 Minor $display change. mohor 6511d 23h /ethmac/tags/rel_15/rtl/
211 Bist added. mohor 6511d 23h /ethmac/tags/rel_15/rtl/
210 BIST added. mohor 6511d 23h /ethmac/tags/rel_15/rtl/
204 ETH_VIRTUAL_SILICON_RAM supported (for ASIC implementation). mohor 6528d 21h /ethmac/tags/rel_15/rtl/
203 Virtual Silicon RAM might be used in the ASIC implementation of the ethernet
core.
mohor 6528d 21h /ethmac/tags/rel_15/rtl/
202 CsMiss added. When address between 0x800 and 0xfff is accessed within
Ethernet Core, error acknowledge is generated.
mohor 6531d 22h /ethmac/tags/rel_15/rtl/

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