URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [tags/] [rel_15/] [rtl/] [verilog/] - Rev 273

Rev	Log message	Author	Age	Path
238	Defines fixed to use generic RAM by default.	mohor	7860d 22h	/ethmac/tags/rel_15/rtl/verilog/
236	State machine goes from idle to the defer state when CarrierSense is 1. FCS (CRC appending) fixed to check the CrcEn bit also when padding is necessery.	mohor	7863d 03h	/ethmac/tags/rel_15/rtl/verilog/
232	fpga define added.	mohor	7868d 22h	/ethmac/tags/rel_15/rtl/verilog/
229	case changed to casex.	mohor	7874d 19h	/ethmac/tags/rel_15/rtl/verilog/
227	Changed BIST scan signals.	tadejm	7874d 23h	/ethmac/tags/rel_15/rtl/verilog/
226	Igor added WB burst support and repaired BUG when handling TX under-run and retry.	tadejm	7875d 01h	/ethmac/tags/rel_15/rtl/verilog/
221	TxStatus is written after last access to the TX fifo is finished (in case of abort or retry). TxDone is fixed.	mohor	7879d 00h	/ethmac/tags/rel_15/rtl/verilog/
219	txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file, TxDone and TxRetry are generated after the current WISHBONE access is finished.	mohor	7882d 01h	/ethmac/tags/rel_15/rtl/verilog/
218	Typo error fixed. (When using Bist)	mohor	7882d 03h	/ethmac/tags/rel_15/rtl/verilog/
214	Signals for WISHBONE B3 compliant interface added.	mohor	7883d 00h	/ethmac/tags/rel_15/rtl/verilog/