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[/] [ethmac/] [tags/] [rel_15] - Rev 246

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246 Since r_Rst bit is not used any more, default value is changed to 0xa000. mohor 7864d 23h /ethmac/tags/rel_15
245 Rev 1.7. mohor 7865d 17h /ethmac/tags/rel_15
244 r_Rst signal does not reset any module any more and is removed from the design. mohor 7865d 19h /ethmac/tags/rel_15
243 Late collision is not reported any more. tadejm 7866d 00h /ethmac/tags/rel_15
242 Late collision is reported only when not in the full duplex.
Sample is taken (for status) as soon as MRxDV is not valid (regardless
of the received byte cnt).		 tadejm 7866d 15h /ethmac/tags/rel_15
241 StartIdle state changed (not important the size of the packet).
StartData1 activates only while ByteCnt is smaller than the MaxFrame.		 tadejm 7866d 15h /ethmac/tags/rel_15
240 All modules are reset with wb_rst instead of the r_Rst. Exception is MII module. tadejm 7866d 15h /ethmac/tags/rel_15
239 RxError is not generated when small frame reception is enabled and small
frames are received.		 tadejm 7866d 15h /ethmac/tags/rel_15
238 Defines fixed to use generic RAM by default. mohor 7878d 19h /ethmac/tags/rel_15
236 State machine goes from idle to the defer state when CarrierSense is 1. FCS (CRC appending) fixed to check the CrcEn bit also when padding is necessery. mohor 7881d 00h /ethmac/tags/rel_15
235 rev 4. mohor 7881d 15h /ethmac/tags/rel_15
234 Figure list assed to the revision 3. mohor 7881d 23h /ethmac/tags/rel_15
233 Revision 0.3 released. Some figures added. mohor 7882d 00h /ethmac/tags/rel_15
232 fpga define added. mohor 7886d 19h /ethmac/tags/rel_15
231 Description of Core Modules added (figure). mohor 7888d 20h /ethmac/tags/rel_15
229 case changed to casex. mohor 7892d 17h /ethmac/tags/rel_15
227 Changed BIST scan signals. tadejm 7892d 20h /ethmac/tags/rel_15
226 Igor added WB burst support and repaired BUG when handling TX under-run and retry. tadejm 7892d 22h /ethmac/tags/rel_15
225 Some minor changes. tadejm 7892d 22h /ethmac/tags/rel_15
224 Signals for a wave window in Modelsim. tadejm 7892d 23h /ethmac/tags/rel_15
223 Some code changed due to bug fixes. tadejm 7892d 23h /ethmac/tags/rel_15
221 TxStatus is written after last access to the TX fifo is finished (in case of abort
or retry). TxDone is fixed.		 mohor 7896d 21h /ethmac/tags/rel_15
219 txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,
TxDone and TxRetry are generated after the current WISHBONE access is
finished.		 mohor 7899d 22h /ethmac/tags/rel_15
218 Typo error fixed. (When using Bist) mohor 7900d 00h /ethmac/tags/rel_15
217 Bist supported. mohor 7900d 00h /ethmac/tags/rel_15
216 Bist signals added. mohor 7900d 00h /ethmac/tags/rel_15
215 Bist supported. mohor 7900d 01h /ethmac/tags/rel_15
214 Signals for WISHBONE B3 compliant interface added. mohor 7900d 21h /ethmac/tags/rel_15
213 Defines changed to have ETH_ prolog.
ETH_WISHBONE_B# define added.		 mohor 7900d 21h /ethmac/tags/rel_15
212 Minor $display change. mohor 7900d 21h /ethmac/tags/rel_15

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