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Rev Log message Author Age Path
214 Signals for WISHBONE B3 compliant interface added. mohor 7869d 01h /ethmac/tags/rel_16
213 Defines changed to have ETH_ prolog.
ETH_WISHBONE_B# define added.		 mohor 7869d 01h /ethmac/tags/rel_16
212 Minor $display change. mohor 7869d 01h /ethmac/tags/rel_16
211 Bist added. mohor 7869d 01h /ethmac/tags/rel_16
210 BIST added. mohor 7869d 01h /ethmac/tags/rel_16
209 Just back-up; not completed testbench and some testcases are not
wotking properly yet.		 tadejm 7870d 04h /ethmac/tags/rel_16
208 Virtual Silicon RAMs moved to lib directory tadej 7885d 22h /ethmac/tags/rel_16
207 Virtual Silicon RAM support fixed tadej 7885d 22h /ethmac/tags/rel_16
206 Virtual Silicon RAM added to the simulation. mohor 7885d 23h /ethmac/tags/rel_16
205 ETH_VIRTUAL_SILICON_RAM supported. mohor 7885d 23h /ethmac/tags/rel_16
204 ETH_VIRTUAL_SILICON_RAM supported (for ASIC implementation). mohor 7885d 23h /ethmac/tags/rel_16
203 Virtual Silicon RAM might be used in the ASIC implementation of the ethernet
core.		 mohor 7885d 23h /ethmac/tags/rel_16
202 CsMiss added. When address between 0x800 and 0xfff is accessed within
Ethernet Core, error acknowledge is generated.		 mohor 7889d 00h /ethmac/tags/rel_16
201 Core size added to the document. mohor 7889d 01h /ethmac/tags/rel_16
200 File with lower case checked in instead. mohor 7889d 01h /ethmac/tags/rel_16
199 Datasheet name changed to lower case name. mohor 7889d 01h /ethmac/tags/rel_16
198 Removed file. File with name in lower case will be added instead. mohor 7889d 01h /ethmac/tags/rel_16
197 Ethernet Data Sheet. mohor 7889d 01h /ethmac/tags/rel_16
196 Ethernet product brief. mohor 7889d 02h /ethmac/tags/rel_16
195 Product brief removed because it is the same as Datasheet. mohor 7889d 03h /ethmac/tags/rel_16

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