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[/] [ethmac/] [tags/] [rel_16/] - Rev 236

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236 State machine goes from idle to the defer state when CarrierSense is 1. FCS (CRC appending) fixed to check the CrcEn bit also when padding is necessery. mohor 7864d 04h /ethmac/tags/rel_16
235 rev 4. mohor 7864d 19h /ethmac/tags/rel_16
234 Figure list assed to the revision 3. mohor 7865d 03h /ethmac/tags/rel_16
233 Revision 0.3 released. Some figures added. mohor 7865d 03h /ethmac/tags/rel_16
232 fpga define added. mohor 7869d 22h /ethmac/tags/rel_16
231 Description of Core Modules added (figure). mohor 7872d 00h /ethmac/tags/rel_16
229 case changed to casex. mohor 7875d 20h /ethmac/tags/rel_16
227 Changed BIST scan signals. tadejm 7876d 00h /ethmac/tags/rel_16
226 Igor added WB burst support and repaired BUG when handling TX under-run and retry. tadejm 7876d 01h /ethmac/tags/rel_16
225 Some minor changes. tadejm 7876d 02h /ethmac/tags/rel_16
224 Signals for a wave window in Modelsim. tadejm 7876d 03h /ethmac/tags/rel_16
223 Some code changed due to bug fixes. tadejm 7876d 03h /ethmac/tags/rel_16
221 TxStatus is written after last access to the TX fifo is finished (in case of abort
or retry). TxDone is fixed.		 mohor 7880d 01h /ethmac/tags/rel_16
219 txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,
TxDone and TxRetry are generated after the current WISHBONE access is
finished.		 mohor 7883d 02h /ethmac/tags/rel_16
218 Typo error fixed. (When using Bist) mohor 7883d 04h /ethmac/tags/rel_16
217 Bist supported. mohor 7883d 04h /ethmac/tags/rel_16
216 Bist signals added. mohor 7883d 04h /ethmac/tags/rel_16
215 Bist supported. mohor 7883d 04h /ethmac/tags/rel_16
214 Signals for WISHBONE B3 compliant interface added. mohor 7884d 00h /ethmac/tags/rel_16
213 Defines changed to have ETH_ prolog.
ETH_WISHBONE_B# define added.		 mohor 7884d 00h /ethmac/tags/rel_16

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